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JUNE 2018 I DESIGN007 MAGAZINE 43 small, all subsequent reflections will be negligi- ble. However, in this case, the reflection causes a non-monotonic edge at the first receiver (orange waveform), which could lead to false triggering of the receiver. If for example, there are four memory chips on the address line, then this would occur on all receivers except the last to a similar extent. Figure 3 illustrates a typical DDR3 fly-by topology with the termination at the very end of the final load. Also, the passing address sig- nal trace goes directly to the receiver pins with no stub. This is the ideal scenario. In this case, there are no reflections, from the termination, which can be seen from the waveforms. Now let's add a half inch stub from the pass- ing address signal trace going to each receiver input pin, as I have seen many designers do. Figure 4 shows the schematic and the resul- tant waveforms. The reflections created by the additional capacitance, of the stubs, is not quite as bad as that of Figure 2, which had the termination before the final load. However, this demonstrates the impact of stubs on the ACC signals in the fly-by topology. Figure 5 shows the jitter and noise created by the half inch stubs on the signal. After running a few more, quick simula- tions in HyperLynx LineSim with varying stub lengths, I found that the stub length can be no more than 200 mil, to alleviate the impact of the reflections, in this (typical) case. This results in the reasonably clear eye diagram of Figure 6. In conclusion, DDR3/4 fly-by parallel termi- nations should be placed after the last receiver at the end of the transmission line and routed directly to the last receiver. Since there is no reflection from this topology, this implies that the length, from last receiver to the termina- Figure 3: DDR3 fly-by topology with termination after final load.

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