Issue link: https://iconnect007.uberflip.com/i/1176876
OCTOBER 2019 I PCB007 MAGAZINE 71 On the topside, we have a maximum stub length of 0.125 mm. Here, we do not have to include the 0.1 mm bottom side of the slot. The top side of the slot is overplated (after filling the trench with a dielectric), as shown in Figure 8. The cap plating is optional (Figure 8) on the top of the back-routed VeCS element. If this is applied, then it could influence the impedance and need to be taken into the simulation as a design parameter (Table 1). The dielectric in the centre of the board (thickness 1.0 mm) can be varied to adjust the vertical trace length to determine the influence on the signal performance. Now, it is used as a filler to save on processing unused inner lay- ers. The filling material used for the slot is a via filling/plugging ink. The properties in the frequency dome are known and can be used in a field solver model to create an accurate model. Signal Integrity Analysis of the VeCS Stitching Element Escaping out of a connector or BGA is one complexity factor; there are also options to cre- Figure 7: Stub length at the top. Figure 8: The top side of the overplated slot. Table 1: Stackup.