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46 DESIGN007 MAGAZINE I APRIL 2022 count, and weight of electronics products, as well as provide significant RF benefits. Figure 1 shows the trace width for the available tech- nology processes. e smartphone, tablet, and wearables mar- kets have advanced the mSAP processes to be compatible with high volume PCB fabrication. Current designs merge both subtractive-etch processing and mSAP processing. is combi- nation is crucial to the thinner, smaller moth- erboard design which frees up space for a more robust battery. A technology teardown of the Gen 11 iPhone X shows trace/space designed at 1.2 mils (30 mm) and more advanced designs have 0.4 mils (10 mm) features. at is a com- plete game-changer for PCB design. SAP provides tighter line width control and straight conductor sidewalls, greatly improv- ing impedance control. In a subtractive pro- cess, fine lines are formed by coating the cop- per layer with an etch resist where the cop- per should be retained and etching away the remaining copper. e main drawback of this approach is that the chemical etchant used to vertically etch the lines will also dissolve the copper in the trace walls. In a cross-section view, the resulting traces will appear trapezoi- dal (Figure 2). With SAP, a much thinner copper layer is coated onto the laminate and plated in the areas where the resist is not applied. e thin copper remaining in the spaces between conductors is then etched away. e traces are formed with much greater precision, in straight vertical lines, yielding an almost rectangular-shaped cross-section that maximizes circuit density and enables accurate impedance control with lower signal loss. With traditional subtractive etch processes, controlled impedance is typi- cally specified with a ±10% tolerance due to variation in the material and the process. With SAP, the line width tolerances are much more tightly controlled and controlled impedance can be held to a stricter tolerance. e standard SAP process utilizes some roughening or texturing of the dielectric sub- strate to achieve sufficient adhesion; however, the rough surface at the plating/resin interface potentially increases transmission loss at high signal speeds. To promote the signal integrity of high-frequency signal transmission, the SAP process should provide high plating-to-resin adhesion as well as a very smooth interface in between. Consequently, the copper roughness should be kept under 1 µm. Routing channels between BGA ball con- tact lands is progressively restricted as the contact pitch is reduced. Some suppliers of FPGAs understand the challenges facing the PCB designer in signal routing and have main- tained a constant 0.30 mm contact diameter to maximize conductor routing channels on the outer surface of the circuit board. Even though smartphones and tablets may have stabilized in size and the trend is more toward system- in-chip than it is toward further shrinking, we definitely will be seeing more chips with pitches of 0.3 mm and less. Generally, PCB designers can only route to the outer two rows of lands on the perimeter of a BGA using HDI technology. Squeezing one signal trace between BGA lands or break- Figure 2: Trace geometry for the subtractive (left) and additive processes (right).