Issue link: https://iconnect007.uberflip.com/i/1464168
APRIL 2022 I DESIGN007 MAGAZINE 47 out vias has been the unofficial limit for typi- cal low-cost multilayer boards for many years. Although, if you choose to pay a premium, then the limits can always be stretched as in Figure 3 (right). However, the SAP process promises greater freedom with six 1/1 mil trace/space between lands. Figure 3 (le) is a drawing of multiple traces routed between 0.3 mm pitch lands. However, this may be push- ing the limit, not because of physical size, but rather because of signal integrity requirements for impedance and coupling. ere are a few issues with tightly routed signal traces: 1. Unintentional coupling of parallel segments is extremely strong between 1-mil spaced traces. is might be fine for grouped synchronous buses and data lanes but horrendous for unrelated signals. Figure 4 illustrates the exponential increase in crosstalk with tight coupling, particularly on outer microstrip layers. 2. e impedance of the trace must be maintained at 40–50 ohms and this is not possible with the standard dielectric thickness of HDI stackups. An extremely thin dielectric of 1 mil or less is required to maintain 50 ohms impedance with a 1-mil trace; this technology may not be suitable for standard HDI rigid boards. However, flexible circuits are ideal with Apexyl LPEN/LPET, Dupont Pyralux Flex, in- Flex A/H, Ultrflex GTS 7800, and Rogers Figure 3: SAP (left) vs. HDI routing (right). (Source: Averatek) Figure 4: Crosstalk vs. spacing for microstrip and stripline layers.