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SEPTEMBER 2022 I PCB007 MAGAZINE 61 Shaughnessy: One of the crazy things about this was that a lot of these vias were failing during reflow, but then the open was closing back up. It would come out as a pass and then it would get into the field and fail. Is that still happening? Partida: We affectionately call that self-heal- ing. During reflow, usually an open on a micro- via will happen as we approach the very peak of the reflow temperature. erefore reflow testing and resistance monitoring is so critical and important. e event of the open is very short and it's wide open. It's not like a resist. It's open, but it's only at 10 or 15 degrees of the peak reflow that this happens. It goes open and then it re-connects. What happens is that the material compresses back down and just recon- nects. Once it's gone open, a separation exists. It is so small you can't see it at 500x sometimes. So, when it cools down, it just compresses and makes contact at room temperature. But once the component comes up to the temperature, it can create a slight gap in resistance and if you're doing super high-speed digital, it's really an RF carrier and signal. If you have a gap, it's just going to ruin the signal. Shaughnessy: is is pretty huge news. I know a lot of really smart people have been looking at this issue over the past few years. Partida: I just want to share what we've learned. It is possible to stack microvias, sometimes. You have to simulate, though. Johnson: ank you, Gerry. We appreciate this. Partida: ank you for the opportunity. PCB007 WHITE PAPER EXCERPT: Next Progression in Microvia Reliability Validation— Reflow Simulation of PCB Design Attributes and Material Structural Properties During the PCB Design Process To understand how best to address the failures of microvias, it's useful to go back into history. And, in particular, to start with the test method process. Historically, PCB fabrication and delivery of fin- ished products preceded test methods to validate the finished PCB. In the 1970s, PCBs were fabri- cated and shipped without electrical test (ET) valida- tion. At the beginning of the 1980s, electrical testing became standard and a requirement for all but the simplest products. For the next decade, PCBs were built by using a "Golden" board programming. The Golden board method used a finished PCB from a finished lot of boards, and it was placed on a test fix- ture by an operator who would then initiate a self- learned shorts and opens program from the board. If the second PCB matched the first, a Golden board was established. One of the shortcomings of the Golden board testing was that it was susceptible to missing the errors in the fabrication data that had been supplied. This method would also allow for CAM errors to go undetected up to assembly. A solu- tion finally came about when CAM and net list com- pare was made available in the late 1980s. In this process, software was used to validate the received data before fabrication started and then the same software was used to generate an ET program to validate the finished PCB. This method saved prod- uct cycle time, prevented the loss of material, and Editor's note: This paper was presented and published for the 2022 IPC APEX EXPO Technical Conference in San Diego, California, and is reprinted with permission from the author. Gerry Partida, SUMMIT INTERCONNECT

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