Issue link: https://iconnect007.uberflip.com/i/1490123
40 PCB007 MAGAZINE I JANUARY 2023 products feature multiple advanced packaging technologies, including die stacked on differ- ent die, die embedded into the package, mul- tiple die stacks attached to the package, and an advanced thermal solution. is "mix and match" architecture gives product designers the flexibility to deliver the best products. Across all these manufacturing stages, dem- onstrating economic viability for domes- tic manufacturing will require dramatic changes to how factories and process tools are designed. Output per tool must improve signif- icantly, while labor content needs to decrease significantly—each by an order of magnitude. is represents both a challenge and an oppor- tunity for the industry and should become an area of focus for programs launched under the CHIPS Act. Ensuring the final packaged products meet the stringent quality and defect levels requires significant testing—both in-line and at end of line. With current products requiring 100 bil- lion transistors and projections calling for 1-trillion-transistor products around 2030, the challenge is large. ese products have tight performance targets and must be able to per- form under broad use conditions. Yield management with multiple die in one unit requires performing high levels of test cov- erage and defect management within the pro- cess flow. e cost impact of yield loss is sig- nificant. Testing for advanced packaging has the unique characteristic of needing to test and verify the performance and reliability of all die ahead of package assembly. Rather than simply sorting wafers to look for gross fab defects, die testing needs to test for both fab defects and some performance characteristics; further, this process needs to stress not only individual die, but stacks of die as well. Post-assembly, devices must be tested for assembly defects, stressed, classified, and run at the system level for optimal performance characterization, as well as quality and reliability verification. In addition, if the final unit is composed of mixed technology node components such as digital, analog, optical, and/or MEMs, the testing methodology is further complicated Figure 1: The Intel® Data Center GPU Max Series, an example of a complex advanced package product.