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24 PCB007 MAGAZINE I JANUARY 2023 different types of chips and components into a single package, manufacturers can create more powerful and efficient devices than ever before. One of the challenges of advanced HI is the complexity of designing and manufacturing these packages. e process requires advanced technologies and specialized equipment, mak- ing it necessary for manufacturers to invest in research and development to stay at the fore- front of this technology. HI utilizes technologies and architectures that allow chiplets to be interconnected in very close proximity to one another, achieving a reduced package area and faster electrical inter- connections between the components. Current HI package structures that are widely imple- mented in the industry include silicon (Si) inter- posers; fan-out wafer level packages (FOWLP) on build-up substrate; and FOWLP packages without substrates, as shown in Figure 2. Silicon interposers provide high-density electrical routing between interconnected chiplets. In Figure 2a, the Si interposer acts as a lateral bridge between the processor die and the stacked memory die. In addition, it pro- vides routing from the high-density chiplets assembled on the top of the interposer to the build-up substrate below using through silicon vias (TSVs). In this package configuration, a build-up substrate is required to provide verti- cal routing between the higher density Si inter- poser and the PCB. Challenges for this pack- age are a reliable source for the Si interposer, a complex assembly process requiring under- fill and high-accuracy chip attach, and manag- ing the stresses due to the coefficient of ther- mal expansion differences between multiple stacking levels. For Si interposers, the CTE will be around 3-4 ppm/°C, while an organic build-up substrate will have CTE ranging from 8-11 ppm/°C; this CTE mismatch will have to be resolved with materials selection and pack- age design. Another solution is to integrate chiplets in a FOWLP package stacked on a build-up sub- strate, which is then mounted to the device PCB (Figure 2b). is package has the advan- tage of eliminating the Si interposer. Now the CTE of the FOWLP package is closer to that of the organic build-up substrate. In addition to eliminating the need for a Si interposer, FOWLP enables the reduction of build-up layers in the substrate. FOWLP Figure 2: Pathways to advanced heterogenous integration using a) silicon interposer; b) fan-out wafer level packaging on build-up substrate; and c) fan-out wafer level packaging without substrates. One of the challenges of advanced HI is the complexity of designing and manufacturing these packages.