Issue link: https://iconnect007.uberflip.com/i/1490123
32 PCB007 MAGAZINE I JANUARY 2023 time. at is an issue known to the industry as "known good die." How the individual dies are tested and validated must be solved. Usually, one only finds out about these issues aer it's too late. Cost Issues Most integrated circuit manufacturers' equip- ment is not ready for the onslaught of advanced packaging. e equipment for such a process is highly specialized and expensive. is spe- cialty requirement is driving up the cost of APT devices on the market. In the future, we should expect that costs should come down. Conclusion Advanced packaging technologies have a bright future. e insatiable appetite that the everyday consumer is looking for and expect- ing from their devices is increasing. It drives this new technology—one that is now main- stream as we finally put to rest Moore's Law and change how we look at the semiconductor industry with a major paradigm shi. Instead of simply looking at increasing node density, we can now customize based on entire sections of circuits for a specific industry and application. It's an exciting time. PCB007 References 1. Advanced Packaging Market Size to Hit Around US$41.8 Bn by 2030," Nov. 10, 2021, GlobeNewswire. 2. "'Moore's Law is dead,' says Gordon Moore, by Manek Dubash, Techworld, April 13, 2005. John Watson, CID, is customer success manager at Altium, a professor at Palomar College, and an I-Connect007 columnist. To read past columns, click here. Download the Altium eBook The Printed Circuit Designer's Guide to… Design for Manufacturing by David Marrakchi. You can also view other titles in our full I-007eBooks library. that particular packaging methods are popular with various industries. For example, high-end AI products such as smartphones and graphic processing units lean more toward 2.5D tech- nology. e industry demands target specific applications and markets with how the various individual circuits are combined with the pack- aging methods. e various methods of advanced packaging are listed below. • Wafer level packaging • 5D and 3D • System-in-package • Bumping and flip-chips • Chip scale packages • Redistribution layers • Embedded die substrate • MESM and microsystem packaging Inherent Problems With APT e APT comes with several inherent prob- lems. First is power dissipation and power use; directly connected to that is the increase and necessity of heat dissipation. Traditionally, sili- con generates a lot of heat and is not thermally efficient. It is now seeing a decrease in voltages, but to maintain or increase the power means an increase in current. How is this power migrated through the package and the heat dissipated? Even just a single chip can have problems with power consumption and heat. Now we com- bine them with other items such as in a system- in-package (SiP) that also holds the micropro- cessor, the flash, and the SRAM all in a single chip. We've just increased the issue exponen- tially. Known Good Die (KGD) When combining the various individual parts, especially when designing a SiP design package, It is unknown whether an individual circuit works until it is in the final package con- figuration. Because specific devices cannot be adequately tested beforehand, the failure rate is high and expensive due to lost production