Issue link: https://iconnect007.uberflip.com/i/1490123
56 PCB007 MAGAZINE I JANUARY 2023 by extensive research at the Georgia Tech Packaging Research Center, now provides very high routing capability comparable with silicon substrates at far lower cost. e com- patibility between the coefficient of thermal expansion (CTE) of glass and Si chips makes for highly reliable, multichip assembly either in a chiplet or SiP application. Finally, bonding and interconnection advances greatly facilitate successful assem- bly employing TSV and very high-density sub- strates. TechLead first developed and dem- onstrated nano bonding as a method of very high-density chip-to-chip interconnection at a 32-micron pitch in 2012. IBM Zurich contin- ued this research from 2013 using nano copper for PWB assembly. At the University of Tokyo, Tadatomo Suga Sensei occupies the forefront of surface activation bonding technology, which now finds its place in various assembly configurations ranging from wafer-to-wafer bonding to chiplet assembly. Consider the implications of the transition from laboratory curiosity to mainstream man- ufacturing capability of TSV and glass/sili- con package substrates. Add the emergence of innovative chip connection technologies, such as nano bonding and surface activation bond- ing to complement traditional reflow assembly, and the possibilities increase exponentially. Together, these technologies enable chiplet architecture as well as expanding SiP (system in package) options such as mixed-chip tech- nology. Chiplets allow more complex component designs from the semiconductor houses that incorporate the optimum IC fabrication tech- niques for each piece of their application. For example, by separating logic, memory, and power distribution into individual chiplets, the designer leverages both layout and fabri- cation technology to maximize miniaturiza- tion as well as performance. Additional gains in thermal management capability, combined with the ultra-high routing density enabled by the combination of TSV and the extremely fine line/space capabilities of glass/Si sub- strates, reduces the total pin count (and gen- erally thereby I/O density) seen by the PWB. Clearly, this greatly simplifies PWB assembly and therefore increases yields. Chiplets also facilitate a "gate array" men- tality for producing enhanced functionality in these components. Rather than restriction to in-house chiplets, the component designer gains access to the best available design and manufacturing for each piece of their com- ponent to further optimize overall function- ality and performance. Not only are internal resource requirements (e.g., design, fabrica- tion, test, etc.) dramatically reduced, but ever- critical time to market reduces dramatically as well. Certainly, the matter of known good die (KGD) remains a barrier, but significant prog- ress during the past three decades reduces this concern to a manageable level in most cases. Standardization efforts within the industry seek to enable and stabilize these opportuni- ties. So, what role does SiP play, the parent of chiplet architecture? Many applications demand mixed device types such as GaAs, SiC, InP, etc., to provide more specialized function- ality that remains difficult to implement with a chiplet design. SiP remains the approach of choice for more complex and/or unique applications where specialized requirements