Issue link: https://iconnect007.uberflip.com/i/1505220
46 DESIGN007 MAGAZINE I AUGUST 2023 see that the impedances of connector and AC coupling pads are below the target and the impedance of the length compensation sec- tions is above the target—a layout mistake. e discontinuities in the reference conductors also create impedance violations—another lay- out mistake discovered by the tool. Figure 3 is another example of the imped- ance continuity analysis for properly localized PCIe link on the OCP board. e analysis is done at the Nyquist frequency of PCIe 5.0 signal running at 32 GT/s. e tar- get differential impedance is 100 ohms, and we can see that the link may require some improve- ments. e question is how the impedance vio- lations affect the signal transmission. Analysis of reflections in 3D SI analysis mode (or Fast SI for lower data rates) can answer that. Accu- rate 3D SI models are used here to compute return loss (RL) and do the TDR analysis as illustrated in Figure 4. e return loss violates PCIe 5.0 standard mask (the black line on the bottom graphs) in this case; the main reasons for that are the Figure 3: Impedance continuity analysis of the OCP board shows impedance violations. Figure 4: Examples of violations, primarily caused by reflections.