Issue link: https://iconnect007.uberflip.com/i/1505220
AUGUST 2023 I DESIGN007 MAGAZINE 45 vias, and via hole localization 4 . Basically, it is the analysis of the current return path. Figure 1 is an example of the reference integrity analysis for all DDR data links on the Open Computing Project (OCP) PCB. e analysis is done for DDR5 data rate 6.4 GT/s and reveals some problems in the nets marked with the red stop signs on the right (severe reference integrity violations). Some traces go over the splits in the closest reference planes and some via holes are un-localized (begin leaking the energy at the Nyquist fre- quency). e severe reference integrity viola- tions must be fixed in layout before proceeding with any other type of analyses. is is impera- tive. e PCB in this case was designed for DDR3 and as we can see cannot be used "as is" for DDR5. When all reference integrity problems are corrected, we can proceed with the other types of compliance analysis. Impedance continuity analysis in ERC mode can be used to quickly check the impedance of interconnects, includ- ing vias and pads. (More on impedance and reflection.) 5,6 Figure 2 illustrates impedance analysis, showing how the reference conductors can change the impedance of traces on a design with traces going through BGA breakouts. e soware evaluated the effect of cut-outs and reference pads on the impedance. We can Figure 1: Reference integrity analysis for DDR data links in the OCP board. Figure 2: Impedance analysis that shows how BGA breakouts can alter impedance of traces.