Issue link: https://iconnect007.uberflip.com/i/1505220
44 DESIGN007 MAGAZINE I AUGUST 2023 integrity or have a PhD in electromagnetics to use it. e first version was introduced in 2007. It was the first electromagnetic tool designed specifically for PCB designers and signal integrity engineers. Since then, its evolution is a chain of innovations in interconnect analy- sis and validation. In the past three years, with the major part of the work completed in "self- isolation," our team has elevated the tool to a new level. Our soware development kit was intro- duced for design exploration, machine learn- ing, and for possible integration into other tools 3 . Post-layout geometry processing, visu- alization and model building were accelerated orders of magnitude. Electromagnetic analysis was also accelerated orders of magnitude with the domain decomposition technique. We had enough time—there were very few distrac- tions—and sufficient expertise to re-think and re-design the post-layout process, making it suitable not only for SI engineers, but for any PCB designer. e result is a tool called the SI Compli- ance Analyzer that can be used for fast, con- sistent post-layout signal integrity verification with simulation-based electrical rule checking (ERC), basic signal integrity analysis (Fast SI), and advanced 3D EM signal integrity analysis (3D SI). It is a solution for interconnect vali- dation and compliance analysis tasks with one unified easy-to-use interface and the following operating modes: • Electrical rule checking (ERC) uses the 2D quasi-static Simbeor field solver (SFS) for traces and component pads and fast EM models of via holes, to find reference integ- rity and localization violations, imped- ance continuity violations, and possible crosstalk noise. is mode can be used for interactive analysis of links in a fraction of a second or thousands of links with auto- mation. It makes all geometry-based rule checkers obsolete and unnecessary. • Fast SI uses SFS for traces and pads, fast EM models of via holes and precise de- composition for the basic signal integrity analysis of crosstalk noise, losses, delay, and skew for relatively slow signals (<10 Gpbs, >100 ps rise time), or preliminary analysis of high-speed links. It enables interactive analysis of links in seconds or hundreds of links with the automation in real time. • 3D SI uses the 2D quasi-static field solver or a 3D EM solver for traces and 3D EM solver for via holes, component pads, and other discontinuities and precise de- composition for advanced signal integrity analysis of PCB/packaging interconnects (unlimited data rates, accuracy depends on geometry, materials, and link localiza- tion). It enables interactive analysis of links in minutes or hundreds of links with the automation in real time. All those modes are designed to verify inter- connect compliance with a particular signaling standard and quickly find the reason for failure if a compliance metric is violated. A few exam- ples of interconnects analysis and optimization are provided to illustrate the process. A perfect digital interconnect is a lossless transmission line with constant characteris- tic impedance and phase delay over the signal bandwidth and termination resistors matching the characteristic impedance. In such inter- connect, bits sent by transmitter would flow smoothly into the receiver with no bit rate lim- its. Such an ideal transmission line is only imag- inary and theoretical. e physics of our world does not allow that. To ensure that the digital signal is actually getting through, we have to build interconnect models that include all sig- nal degradation factors important for a specific data rate. But, before building any model, the reference integrity and via localization must be verified and fixed if necessary. Reference integrity analysis in ERC mode checks all reference conductors and stitching