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78 PCB007 MAGAZINE I JANUARY 2024 In subsequent trials the heavy copper layers were filled using two plys of prepreg on each side of an etched core in a pre-fill lamination step, aer which all the pre-filled cores were bonded together with an additional two plies of prepreg. e secondary reason for selecting this build was that it was well known to have voiding defects in the low-pressure areas and crack- ing in the resin rich areas due to the CTE mis- match between the polyimide resin, copper, and glass reinforcement. e Figure 19 photo was taken aer six 10x solder shocks at 260°C. ere was no evi- dence of cracking due to the lower modulus of the prepreg and the material having a CTE of 20-22ppm/°C, which closely matches to the CTE of copper (18ppm/°C). Figure 20 is an image of the design using a full polyimide build of materials: Conclusion is testing shows that a low modulus, non- reinforced resin system, with a CTE closely matching copper, has many applications with today's more challenging designs. Further work is planned, including lower Dk versions and completion of the work to verify pad cratering can perhaps be eliminated. Summary All the initial trials have been successful and achieved better than expected results. e non- reinforced material(s) have been shown to suc- cessfully function as a thermally reliable build- up material, to fill and flow into mode sup- pression vias and simultaneously act as both a bond ply and via fill, can be used as a leveling agent to afford very flat surfaces for the attach- ment of large ball grid array packages, and can be used to flow and fill extremely thick etched copper layers up to four ounces. PCB007 Acknowledgements Robisan Laboratories carried out all simulated reflow testing. Resources 1. IPC-TM-650 2.6.26 Method A, Test Methods Manual. 2. IPC TM-650-2.6.26B, TM-650-2.6.27A and TM-650 2.6.7.2 Test Methods Manual. 3. "The Keys to 100% Effective Reliability Test- ing and Failure Analysis of HDI/Microvias," by Kevin Knadle, IPC APEX EXPO 2020. 4. Avishtech, Gauss 2D, Gauss Stack, 5491 Opti- cal Court, Suite 215, San Jose California. 5. "The Next Generation high-Tg products for Telecom and Broadband Applications," by S. Mir- shafiei, November 2004. 6. "Highly Accelerated Thermal Shock (HATS) Reliability Testing," by Bob Neves, et al, Proceed- ings, IPC Printed Circuit Expo, March 2003. 7. "Understanding IST Technology," by Gerard Gavrel, PWB Corp. 8. "IPC Technology Solutions White Paper on Per- formance-Based Printed Board OEM Acceptance. Via Chain Continuity Reflow Test: The Hidden Reli- ability Threat—Weak Microvia Interface," by J. Mag- era, et al, IPC-WP-023, May 2018. 9. "Copper Filled Microvias—The New Hidden Threat," by J. Magera, and J.R. Strickland, IPC APEX EXPO 2019. 10. "Nanovoid Formation at Cu/Cu/Cu Intercon- nections of Blind Microvias: A Field Study," by T. Bernhard, L. Gregoriades, S. Branagan, L. Stamp, E. Steinhäuser, R. Schulz, F. Brüning, International Symposium on Microelectronics Proceedings 2019. 11. "The formation of nano voids in electroless Cu layers," by T. Bernhard, S. Branagan, MRS Spring conference, 2019, submitted to MRS Advances 2019. 12. "The Effect of Cu Target Pad Roughness on the Growth Mode and Void Formation in Electroless Cu Films," by S. Zarwel, T. Bernhard, E. Steinhäuser, S. Kempa, F. Brüning F, IWLPC Proceedings, 2019. Figure 20: Cross-sectional image showing typical cracking in polyimide heavy copper designs.