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90 PCB007 MAGAZINE I FEBRUARY 2024 e four conditions are: • Wd > Wc: ere are not enough wires to complete the design • Wd = Wc: Ideal, but nearly impossible to achieve in the time allotted • Wd < Wc: About 20% is a good target to set, especially if autorouting • Wd<< Wc: e normal situation where extra layers are used or tighter design rules than are required 1. Wiring demand > Substrate capacity: If the substrate capacity is not equal to the demand, the design can never be finished. ere is not enough room for either traces or vias. To correct this, either the substrate has to be bigger, or components have to be removed. 2. Wiring demand = Substrate capacity: While optimum, there is no room for variability and to complete the design will take an unacceptable amount of time. 3. Wiring demand < Substrate capacity: is is the condition to shoot for. ere should be enough extra capacity to complete the design on time and with only a minimum of overspecification and costs. 4. Wiring demand << Substrate capac- ity: is is the condition that usually pre- vails. By PC layout, the schedule is tight, and timing is all-important. Many choose tighter traces or extra layers to help shorten the layout time. e impact of this is to increase the manufacturing costs 15–50% higher than is necessary. is is sometimes called the "sandbag approach." It is unfortunate since the models above would help to create a more planned environment. Component Wiring Demand Wiring demand is the total connection length required to connect all the parts in a cir- cuit. When you specify an assembly size, then you create the wiring density in inches per square inch. Models early in the design plan- ning process can estimate the wiring demand. ree cases can control the maximum wiring demand: 1. e wiring required to break out from a component like a flip chip or chip scale package. 2. e wiring created by two or more components tightly linked, say a CPU and cache or a DSP and its I/O control. 3. e wiring demanded by all integrated circuits and discretes collectively. ere are models available to calculate the component wiring demand for all three cases. Since it is not always easy to know which case controls a design, I usually must calcu- late all three cases to see which one is the most demanding and thus controls the layout. e model I find most useful for Case 3 is Coors and Anderson's "Statistical Wiring Requirement." 1 e other widely used models are: • D.P. Seraphim, R. Lasky, and C.Y. Li 2 • H. Ohdaira, K. Yoshida, and K. Sassoka 3 • W. Donath 4 • S. Sutherland and D. Oestreicher 5 • L. Moresco 6 Coors and Anderson's Density Model In 1990, Drs. Paul Anderson, Grover Coors, and Lori Seward of the Colorado School of Mines proposed a statistical model for deter- mining the total wiring requirements (Wd) for a modern digital PWB based on the stochastic model of wiring involving all terminals, their probability of length based on the distance of the second terminal (their probability distribu- tion function), and the special geometry of the other terminals. By benchmarking existing suc- cessful PWB digital designs, the typical multi- layer (Figure 3a) had the net length distribu- tions seen in Figure 2a. is matches the prob- ability distribution function (PDF) in mathe- matics, as seen in Figure 2b. Using a Gamma distribution function, the nets in the real board (Figure 2a) create the interconnect length his- togram in Figure 3b. is model allows the cal-