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68 PCB007 MAGAZINE I FEBRUARY 2024 ganate desmear. Conventional electroless cop- per requires a micro-roughened resin surface to effect sufficient adhesion of the copper to the resin. In contrast, the carbon-based sys- tems are likened to a coating technology. Sur- face topography is not an issue for these car- bon-based systems to adhere to the resin mate- rials. With respect to electroless copper, a pre- cious metal catalyst (palladium is most com- mon) is required to bring about the oxidation of formaldehyde (the reducing agent most commonly used in electroless copper formu- lations). Essentially, electroless copper com- prises two half-cell reactions, with several pro- cess steps required to provide a void-free cop- per deposit. In addition, during the copper plating pro- cess, hydrogen gas is evolved. Hydrogen gas produces bubbles that can lodge in small diam- eter through-holes and blind vias. If the hydro- gen gas bubbles are not efficiently evacuated from the vias, plating voids will result. e overall electroless copper reaction is shown below: Overall reaction: Cu(EDTA) 2- + 2HCHO + 4OH - → Cu + H 2 + H 2 O + 2CHOO - + EDTA 4+ In addition, the manufacturing cycle time to metalize a printed circuit board through a con- ventional electroless copper process is 45–55 minutes. CapEx requirements aside, direct metallization offers faster throughput and, in turn, reduces energy costs as well as green- house gas emissions. Certainly, sustainabil- ity should be on everyone's list going forward. If one simply calculates the amount of energy required to heat process tanks and the time it takes to process a circuit board through any one process, it can be shown that processes that reduce production time and use less energy will reduce the carbon footprint and thus greenhouse emissions. More on this in a future column. Ideal Applications for Direct Metallization With more emphasis on HDI and ultra HDI, ease of use and speed are critical operational must-haves. Advanced packaging is driving higher densities for IC substrates, interpos- ers, and product boards. is necessitates the increased complexity of these boards and sub- strates with ever finer lines and spaces, multi- ple sequential laminations, and smaller diame- ter blind vias. e carbon- and graphite-based Figure 1: Examples of stacked vias.