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90 PCB007 MAGAZINE I APRIL 2024 Wiring Model In 1994, StorageTek, an OEM in Colorado, conducted performance benchmarking with microvia designs and fabrication 2 . e successes of that program contributed to its continued use of microvias. In 1998, it became apparent that they required some wiring model to indi- cate that a microvia structure was required. In performing that model development, a power mesh benchmark was designed for one of the microvia boards 3 . Figure 5 shows the two inner layers of the four-layer power mesh structure and two of the six inner layers from the origi- nal eight-layer through-hole design. e wiring density model for the PMA is: Power Mesh = 17 to 40 signal inches per square inch per layer (dependent on trace width and spacings) • Calculate the Statistical Wiring density using Coors, Anderson & Seward 4 • Calculate the Manhattan Wiring Den- sity using Wd=0.0068(X)^2 – 0.1644(X) + 35.1, where X is the Coors Statistical Wir- ing Density • Calculate the Routability Index for Power Mesh 3 • Calculate the Layout Efficiency using: L.E.(%)= 4.0642(RI)^-1.189, where RI is the Routability Index Summary e microvia topologies of power mesh have demonstrated the application to simplifying complex multilayer, PBGAs, and MCMs. IMPS can reduce the structure to a two-metal inter- connect, while power mesh uses a four-layer reinforced laminate structure. ese results show that these topologies have the capacity of positively impacting how electronic products are packaged and Interconnected. PCB007 Figure 5: Power mesh example at StorageTek provided coefficients for density models: a) The two PMA inner layers compared to b) two of the six inner layers of the original eight-layer TH design; c) circuit side view and cross-section view of the finished power mesh board.