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52 SMT007 MAGAZINE I SEPTEMBER 2024 Article by Neil Hubble, AKROMETRIX and Gary A. Brist, INTEL CORPORATION Editor's Note: is paper was originally pub- lished in the Proceedings of IPC APEX EXPO 2024. Background As CPU and GPU packages grow larger and contain higher pin/ball counts, the importance of managing the printed circuit board (PCB) surface coplanarity for package assembly increases. e PCB surface coplanarity under a package is a product of both the global bow/ twist of the PCB and the local surface topog- raphy under the package. In general, the sur- face topography is dependent the choice of material and layer stackup and the interaction between the innerlayer copper patterns and prepreg resin flow. Advances in chiplet design and heteroge- neous integration solutions in electronic pack- aging are enabling complex packages with increasing total die areas, resulting in the need for larger CPU and GPU packages 1 . Based on trends and advances in package integration, it is expected that future packages exceeding 100–120 mm on a package edge will become more common. is increases the challenge of the second-level interconnect (SLI) assem- bly processes when attaching the package to the PCB due to the combined coplanarity and topography variations of the PCB and package. ese combined influences between the PCB and package are the key drivers of SLI defects such as solder bridging or solder joint opens during PCB assembly. 2,3 Figure 1 is a graphical depiction of how the global PCB warpage or curvature under the package must be smaller for larger packages to achieve the same PCB coplanarity under the package. e characterization of PCB coplanarity under the package footprint has been studied historically, including influences of assembly temperatures on dynamic PCB coplanarity as the PCB and package move together through the assembly reflow temperature profile. 4,5,6 PCB Surface Topography and Copper Balancing Under Large Form Factor BGAs Figure 1: PCB coplanarity under package.