Issue link: https://iconnect007.uberflip.com/i/1526407
14 DESIGN007 MAGAZINE I SEPTEMBER 2024 ing 100-picosecond edge rates. When you have that fast of an edge rate, the harmonic fre- quency content to get that sharp of an edge is hundreds, not tens, of harmonics. e old rule of thumb was, "To reproduce a square wave, you need 10 to 15 harmonics at the fundamen- tal." You could have a 100-kHz signal and have no problem. at same 100-kHz signal now has gigahertz of frequency content to create that sharp of an edge. Regardless of what you're running your clock frequency at, you've got these effectively RF-level frequency harmonics in your signals, which now you have to deal with at the board and chip levels. In the past, we could put a surface mount series termination resistor for overshoot and undershoot and single integ- rity. Now, we have to go to embedded resis- tors because our transition electrical length is on the order of 50 or 100 mils. If we're under a BGA, we can't get a physical resistor close enough to be effective anymore. All of these things are happening to our design because the silicon keeps shrinking. is makes the effective distances we can travel before we need signal integrity—and what we must do to mitigate the signal integrity challenges— orders of magnitude more challenging for the designer. This leads us into packaging. Devan, what should PCB designers know about packaging? Iyer: Kris started talking about it from the point of signal and power integrity analysis, and EMI. ose are fundamental to high- speed digital, RF, and mixed-signal designs. Added to that, one needs to look at co-design and carefully address, thermal management as well. We are dealing with higher voltage and higher power dissipating devices along with low-power dissipating devices in a very small area, which leads to high-power density. Designers oen think, "My device is a low- power device, so it doesn't matter." But if it's dissipating through a very small area, then it becomes a high-power density challenge. You must determine how to take the heat out of the chip through the back edge to the fore: low- power devices with a high power density all the way through medium-power, real high- power devices where we have kilowatts of power being dissipated using silicon IGBT and silicon carbide devices on EV vehicles today. You might be integrating an optical device with an electronic device in a co-packaged optics configuration. Or you may have a fiber assembly that must be dealt with at the package or board level for heterogeneously integrated packages. How do you deal with the mechani- cal stress or thermo-mechanical stress that is generated on the package, the board, and assembly? ere are also issues like high-speed digital design and RF millimeter wave transi- tions, EMI shielding, thermal management and thermo-mechanical stress mitigations. Moyer: In my class, we touch on thermal management from a higher level. We don't have access in my class to a $1 million suite of ANSYS tools to do proper thermal simula- tions, but we have discussions about thermal analysis. Even though you're dissipating only a low amount of power, because it's in such a small area now, it's still a high-power density, Devan Iyer