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54 DESIGN007 MAGAZINE I SEPTEMBER 2024 fer," allowing the ultra-fine-pitch semiconduc- tor die to be expanded to a wider-pitch BGA format. e interposer may also be used to re-route the terminal pattern of one manufac- turer's semiconductor to match the terminal pattern of a product having the same function developed by another manufacturer. A secondary function is to provide a wider pitch terminal interface on the interposer lower surface to better enable signal, power and ground interface with the lower circuit density package substate. Individual die ele- ments arranged on the 2.5D interposer, shown in Figure 2, will each have a unique function and widely diverse physical outlines. e package substrate (most likely the BT- epoxy based or CTE matching laminate) pro- vides additional redistribution of I/O and power/ground terminals to a JEDEC standard ball grid array pattern that will be more com- patible with commercial circuit board fabrica- tion technology. Design Strategy for the 2.5D Interposer A typical 2.5D interposer application sup- ports the interconnect of one very high termi- nal density semiconductor or multiple related die elements. While the upper surface of the 2.5D interposer will accommodate most semi- conductor redistribution and/or die-to-die interface, the primary I/O channels and power and ground terminals are moved to the bottom surface of the interposer. Although the overall circuit density of the 2.5D interposer is signifi- cantly greater than the mainstream HDI circuit board, commercial CAD tools are available to accommodate most very-high-density (VHD) interposer development activity. Developing the high-density interposer substrate can sig- nificantly enhance product performance by enabling much shorter circuit interconnects for critical signal paths. A typical 2.5D interposer for the system-in-package (SiP) applications will probably require interconnecting two or more uncased die elements (oen from mul- tiple sources) within a single package outline. Silicon interposer materials are commonly furnished in a thin round wafer format and sized to comply with the existing semiconduc- tor fabrication infrastructure. Metal deposi- tion processes developed for the silicon-based interposer enable very close coupling between related die elements. e via-hole features on the die-attach side of the interposer may have a pitch in the range of 30-50 microns. Terminal features on the bottom surface are commonly "fanned-out" to a wider 150 to 300-micron pitch. e most common through-silicon-via (TSV) formation process uses a deep reactive- ion etching (DRIE) process (oen referred to as the Bosch process) that can provide vias that range between 5 microns and 20 microns. Guidelines for designing the silicon-based interposer may vary somewhat from one sup- plier to another, but the designer can use the data furnished in Table 1 as a baseline that can be confirmed or altered when discussing the inter- poser fabrication with the designated supplier. A good deal of silicon-based 2.5D interposer products have already been produced but, to sustain a wider acceptance, there remain sev- eral logistical challenges that will need to be addressed: • Cost effective through-silicon-via (TSV) process • in wafer and panel-handling solutions • Lack of a broad 2.5D infrastructure • Technical training for design engineering specialists Figure 2: Three-die, silicon-based interposer application. (Source: Invensas)