Issue link: https://iconnect007.uberflip.com/i/1527613
OCTOBER 2024 I DESIGN007 MAGAZINE 13 Shaughnessy: That's a big advantage. As far as lamination cycles, this is a lot like doing a standard board. at's right. Only the two outer layers are HDI structures. Again, it's just a matter of, "How do I get out of the inner rows?" I'm thinking of things like memory chips and so on, where there is a 0.5 mm pitch, but not a high pitch count. But if it's FPGAs with 400, 800, or 1,200 balls, the only way is with full HDI and full sequential lamination. It's a whole stair-step pattern. With a memory chip that has 16 or 32 or 44 balls, it can be routed out pretty easily. You could do a microvia down one layer, and then go to a target pad there. Once you no lon- ger have to deal with the larger BGA solder ball pads, the rest of the escape route and fanout is pretty easy. If you're doing fine-line geometries and thin copper, the first two rows are routed out on the top surface and then immediately to a via down. Again, with a little bit more room, you can actually get four rows out to the perimeter. Once you're outside the perimeter of that BGA, you can much more easily go to a traditional mechanically drilled via to do the layer transitions using standard routing meth- odologies. LaRont: Kris, you have such thin copper and thin dielectric on the outer layers. Does this affect the way you design the inner layers? ere are trade-offs. e inner layers are just standard technology that could be 2.5 or 5 mils or thicker, and that's dictated by signal integ- rity requirements. What is the transmission line structure you're trying to build? If you're doing 1-ounce copper on all the inner layers, and using Isola 370HR or FR-408, on aver- age, with the thinner dielectrics, prepregs and cores, you could get dielectric constants in the 3.7, 3.8 range. In that case, the math says that the distance between the trace and the plane is 5–7 mils on average for a 50-ohm single-ended impedance, assuming that the thinnest trace width will be in that 5-mil trace width range. is is where the whole challenge comes in. If you try to use a thicker copper—a 1-ounce copper—our fabricators will tell us their stan- dard processing is 1-ounce copper. e mini- mal features you should be willing to etch in 1-ounce copper is 5 mils. is is where the whole trade-off on stackup comes into play. If you want to narrow a trace width, you have to use a thinner copper. A thinner copper is fine in my digital section, but in the analog or power sections, you'll need a wider trace to handle the same current at the same temperature. How do you trade off the geometries you need for signal integrity for a characteristic controlled impedance structure with the geometries you need for thermal and power management in your analog and power stages? is is one of the challenges I talk about in my classes. How do we balance this? LaRont: Of course, then everything speaks to cost, too. How much does partial HDI affect cost? at's one of the nice things about this hybrid construction. Because we're not going to use sequential lamination, it's not a very significant cost adder. It's a single lamination, so the only cost adder is the laser drilling and plating of the microvias. " If you want to narrow a trace width, you have to use a thinner copper. "