Issue link: https://iconnect007.uberflip.com/i/1527613
14 DESIGN007 MAGAZINE I OCTOBER 2024 Shaughnessy: What are the biggest fabrication challenges for partial HDI, and what do designers need to do differently in the design cycle? Now that we're doing thinner dielectrics with- out reinforcement, depending on the fabrica- tor and their capabilities, we now have greater X and Y CTEs. is means thermal, float, mis- registration, and so on. Now that we're doing thinner dielectrics without reinforcement, how do we control the layer-to-layer spacing? How do we accurately etch and maintain those fine-line geometries, just like we would in HDI? is is where the partial or hybrid men- tality comes from. We have to look at the standards—IPC-6016 for fabricators and IPC-2226 for designers. You look at this construction and think, "I'm using thinner coppers and thinner dielectrics now. Here are my new design requirements, fabri- cation allowances, and so on." en, we con- sider some of the limitations from the design and the fabricator's points of view, because we will need to use thinner coppers to get to those features. What's the thinnest copper your fab- ricator is comfortable working with? At the same time, you also must ensure that you get a high yield and a low scrap rate. Shaughnessy: You mentioned that some of the biggest design challenges with partial HDI are thermal capability and current and power capabilities. Talk a little more about that. From our digital side, they should not have any problems as long as designers know what their minimum trace width and minimum trace spacing is allowed for that copper weight from their fabricator; they just need to set up their design rules, characteristics, and profiles and so on accordingly. But therein lies the sec- ond part of the problem. When we go to a thin dielectric, resin-coated copper without the glass, the dielectric constant is much, much lower. So, they have to consider that when they're setting up their profile. But I know many engineers and designers who will still use the average reported dielectric constant that's listed on the datasheet for the series, as opposed to the specific dielectric constant for the prepreg or core layer that they're selecting. en, their material or characteristic imped- ance will be way off. ey'll get an impedance discontinuity, a reflection, an overshoot, an undershoot, and all those signal integrity- related problems. Also, when you're using resin-coated copper, the dielectric thickness is pretty much fixed. You don't have many choices on resin thickness with resin-coated copper. So, if they're based on the dielectric constant and the dielectric thickness, calculate my trace width for characteristic impedance. In fact, the calculated width is less than what the factory says they're willing to etch within that dielectric constant and copper thickness. Now again, you'll run into problems with sig- nal integrity, so that's one challenge. e other two big challenges are on the analog and power side of things. You need 12 microns of copper thickness to meet the digital, and there are a couple of BGAs for a memory array. Let's say we're doing 2-gigabyte memory chips and you want 16, so you need eight of these memory chips. Each one of these mem- ory chips is a fine-pitch BGA—the memory.