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16 DESIGN007 MAGAZINE I OCTOBER 2025 B E YO N D D ES I G N The power distribution network has four major functions: 1. Provides a low-impedance, high-energy supply path to the ICs. 2. Reduces noise on the power supply at the IC die. 3. Minimizes ground bounce—common-mode potential between the IC die and the return path. 4. Reduces electromagnetic radiation from the board's fringing fields. Inductance is the curse of high-speed design. At DC and low frequencies, inductance is negligi- ble and can often be disregarded. However, as sig- nal frequencies and edge rates rise, the limitations of multilayer PCBs become increasingly apparent. Parasitic capacitance and inductance begin to dom- inate, undermining the most fundamental design assumptions. Among these, inductance plays a par- ticularly critical role, affecting nearly every aspect of signal and power integrity, from transient response to impedance control and EMI susceptibility. As signal frequencies and edge rates increase, the AC impedance of the PDN rises, primarily due to the inductance associated with bypass and decoupling capacitors connected to the power and ground planes. Each capacitor inherently includes an equiv- alent series inductance (ESL), which causes its impedance to climb at higher frequencies. Capacitors exhibit their low- est impedance at their self- resonant frequency (Figure 2), which is governed by the inter- play of capacitance, equivalent series resistance (ESR), and equivalent series inductance (ESL). To meet the PDN's tar- get impedance at a specific fre- quency, a capacitor is selected such that, once mounted on the PCB, it resonates at that frequency and presents an impedance equal to its ESR. Placing multiple capacitors in parallel reduces their com- bined ESR, allowing the aggre- gate impedance to approach the desired target level. Moreover, the inductance introduced by the capaci- tor's mounting configuration significantly influences circuit behavior. It arises from three key contributors: 1. The capacitor footprint. 2. Its vertical placement relative to the reference plane. 3. The spreading inductance of the power plane. Together, these elements define the loop geom- etry. Larger loop areas result in higher inductance. Among these, the footprint (land pattern) has the greatest influence on the capacitor's equivalent series inductance (ESL). It encompasses via place- ment relative to the pad, the dimensions of the con- necting traces, and the configuration of vias linking to the power and ground planes. The position of these planes within the PCB stackup determines via length, which directly affects inductance. For high- layer-count stackups, place decoupling capacitors on the same side of the board as the IC to mini- mize via length and loop area. Since inductance is proportional to the magnetic field generated by the loop, reducing loop energy by tightening the geom- etry lowers overall inductance. F i g u re 2 : A c a p a c i to r h a s s e r i e s c a p a c i t a n c e, re s i st a n c e, a n d i n d u ct a n c e ( S o u rc e : i C D P D N P l a n n e r) . ▼