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20 DESIGN007 MAGAZINE I OCTOBER 2025 A rtificial intelligence (AI), together with machine learning (ML), is creating an unprecedented surge of computing and networking infrastructure needs. This, in turn, has dramatically increased the power consumption of computing and networking chips. Traditional design and validation methods no longer seem to cope with the new challenges; a paradigm shift is underway in how we design, optimize, and vali- date our system's power distribution network (PDN). During my career in electronics design, the first paradigm shift happened in the late 1990s, when the central processing units (CPUs) in computers grew in complexity and suddenly required tens of amperes of core current. Very early computer boards (before the 1990s) did not need any spe- cific power distribution design. This is illustrated in Figure 1 (left), which shows a diode-transistor logic (DTL) card from computing equipment made in the 1970s. It was on a two-sided board, with no ground plane and no bypass capacitor. Many of us remember the prevailing rule of thumb from the 1980s: Place a 0.1 μF ceramic capacitor across the power-ground pins of each logic chip, usually in dual-in-line (DIL) package. However, by the mid-1990s, the current transients of CPU core rails required a new approach, and power-ground plane pairs replaced the power-ground traces. As a result, the number and val- ues of bypass capacitors increased, and a system- atic frequency-domain design approach was devel- oped. It was based on a calculated impedance tar- get for the power distribution network 1 . Impedance targets in the 1990s were tens of mil- liohms, which immediately created a challenge for validation, since typical instrument setups for imped- ance measurements were not capable of measur- ing milliohms on working computer boards. To mea- sure milliohms, the two-port shunt-through mea- surement setup was developed 2 , and it has been used ever since. In multilayer PCBs, using one or two plane pairs to serve the low-impedance supply F E AT U R E A RT I C L E by I st va n N ova k , S a m te c AI Triggers Next Paradigm Shift in PDN F i g u re 1 : Two - l aye r DT L l o g i c b o a rd f ro m t h e l ate 1 970 s (to p) a n d va l i d at i o n s et u p a n d P D N i m p e d a n c e o n a s e r ve r b o a rd f ro m t h e 2 0 0 0 s ( b ot to m ) . ▼ rails, fortunately, provided low enough series resis- tance that the horizontal power distribution lumped the entire PDN with tolerably low spatial variations. As a reminder: The sheet resistance of a one-ounce copper plane is around 0.7 milliohms, which is low compared to a 10-milliohm parallel target impedance. This was also before the widespread use of dig- ital power converters. As a result, most PDNs dur- ing this period could be treated as linear and time- invariant (LTI) networks, allowing us to use either the time or frequency domain to measure or simulate