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32 DESIGN007 MAGAZINE I OCTOBER 2025 These issues pose significant risks to the opera- tional reliability and overall performance of a device. Intermittent malfunctions, data loss, and reduced lifespan are just some potential consequences of an inadequate PDN. To mitigate these risks and ensure robust performance under demanding conditions, engineers must employ advanced techniques for PDN design and optimization. This includes careful analysis of power requirements, selection of appro- priate components, and rigorous simulation and testing to validate a PDN's ability to maintain sta- ble power delivery across a wide range of operat- ing scenarios. One of the critical parameters in PDN design and optimization is the target impedance, which defines the required impedance threshold for maintaining consistent voltage levels. Target Impedance Requirement Voltage drops seen at device power pins are caused by current flowing through the PDN with a given impedance. To maintain consistent voltage on the pins of a device, the PDN impedance must remain below a defined target impedance, or Z-target. For the Versal adaptive SoC example, the power con- sumption depends on the user's configuration of the device. The AMD power design manager (PDM), shown in Figure 1, is used to derive several critical parameters for calculating the target impedance. The supply voltage of 0.8 V and AC ripple allow- ance of 2% combine with the maximum dynamic current of 100.440 A and a step load percentage of 25% to yield a target impedance of 0.6372 mΩ. This precise target must be maintained across a broad frequency spectrum, particularly in the critical range where decoupling capacitors are most effective. F i g u re 1 : A M D s of t wa re s h ows d y n a m i c c u r re nt a n d ste p l o a d % fo r t h e VC C I N T s u p p l y n et . ▼ Having identified the Z-target, it's time to move forward to the PDN verification process. This essen- tial step allows designers to assess the perfor- mance of a PDN design and ensure that it meets the required specifications. Verification Methodology A systematic verification approach requires models for several key elements of the PDN. First, the voltage regulator module (VRM) is mod- eled using a simplified resistor-inductor circuit, rep- resenting the output impedance the PDN sees from the voltage regulator. This model consists of resis- tance and inductance values that accurately rep-