Issue link: https://iconnect007.uberflip.com/i/1540184
OCTOBER 2025 I DESIGN007 MAGAZINE 35 optimization run produced an alternative solu- tion using 111 capacitors. However, this configura- tion achieved a remarkable 29.53% cost reduction compared to the baseline while providing improved performance margins. The second optimized solution achieved a larger cost reduction despite using more capacitors than the first solution due to the lower-cost parts in the input capacitor library. This highlights the tradeoffs between cost reduction, total part count, and available routing space, which depend on the specific capacitors used in the design. The increased margin proved particu- larly valuable for designs requiring additional robust- ness against variations in operating conditions. Practical Design Considerations The optimized design alternatives highlight several important practical considerations for PDN design. Land-side capacitors, mounted directly beneath the device's bottom layer, prove particularly effective when positioned close to the ball grid array power and ground pins. This strategic placement maxi- mizes capacitor effectiveness by minimizing the length and inductance of the current path. Understanding the frequency-dependent behavior of decoupling capacitors is helpful for effective opti- mization. Below their self-resonant frequency (SRF), capacitors exhibit the expected negative-sloped impedance curve, with impedance decreasing as frequency increases. However, above their SRF, the behavior becomes inductance-dominated, resulting in a positive-sloped impedance curve. This character- istic makes the selection and placement of capacitors particularly critical for maintaining target impedance across the entire frequency range of interest. Parallel resonance frequency (PRF) points require special attention during optimization. When multi- ple capacitors interact, they can create high-imped- ance peaks in the PDN profile, potentially compro- mising the goal of maintaining low PDN impedance throughout the desired frequency range. To meet the target impedance, it is crucial to pro- vide a capacitor part library with a diverse range of capacitor values. This variety allows the optimiz- er's algorithms to select the most suitable parts for the design and account for the PRF interactions between varying capacitors. Additionally, the capac- itor library should only contain parts from approved vendors. Including obsolete or unapproved parts in the library may lead to the optimizer producing results with undesirable or unpurchasable compo- nents, potentially causing issues in the final design. Comprehensive Reporting Modern PDN decoupling tools generate compre- hensive analysis reports that help engineers make informed decisions about their PDN design. A key feature is the loop inductance analysis for each capacitor mounting location, identifying potential placement improvements for better performance. The optimization process considers PDN behavior across the entire frequency range: • DC to 100 kHz: Dominated by VRM and bulk capacitor performance • 100 kHz to 15 MHz: Critical range for local decoupling capacitors • Above 15 MHz: Transition to on-package and on-die decoupling For each design alternative, the optimizer provides detailed recommendations, including optimal capac- itor selection for each mounting location. Unneces- sary capacitor locations are identified and marked as "open" in the termination column, enabling cost reduction and simplified board routing while still meeting the Z-Target requirement. The tool's abil- ity to analyze the complete frequency spectrum is particularly important for high-performance devices like the Versal adaptive SoC, where performance requirements span from DC to the gigahertz range.