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94 I-CONNECT007 MAGAZINE I MARCH 2026 concept, typical of that shown in Figure 1, is not only economical, but it also accommodates unlim- ited design flexibility, significantly reducing system package development time. The basic idea is that modular chips, or chiplets, can be assembled in a package and connected using a die-to-die interconnect of various functions from multiple sources in a single package outline without impacting the underlying structures. Cur- rently, most chiplet package development is led by the semiconductor sector; however, there is a significant surge in independent startups entering the field. For those outside the tent, access to the wide range of general-purpose semiconductors in a chiplet configuration has not been as available as the packaged semiconductors. But it's early, and as soon as the industry establishes uniform standards for common-use chiplet families, chip manufacturers will begin building the supply chain. Key issues for package developers and the circuit design specialist responsible for inter- poser and package substrate preparation are the standards, and whether there will be multiple sources for the primary functional semiconductor building blocks needed to economically create a system-level product. Sure, some of the products are available in a chip-scale or flip-chip configu- ration, but their outline dimensions and terminal pitch are compatible with the projected needs of the system-level package developer. The factors furnished in Table 1, for example, are some of the projected requirements chiplet-configured semi- conductor elements forecasted for current and future applications. Although the chiplet-configured semiconductor may be unfamiliar to the design engineer devel- oping the traditional circuit board-based product, the technology has been implemented by over 130 semiconductor companies, including Alibaba, Advanced Micro Devices, arm, ASE Group, Google Cloud, Intel, Meta, Microsoft, NVIDIA, Qualcomm, Samsung, and TSMC in Taiwan. Together, they have established the Universal Chiplet Intercon- nect Express (UCIe) standard. Multiple Die Interposer Planning Developing the high-density interposer using chiplet technology can significantly enhance prod- uct performance by enabling much shorter circuit interconnects for critical signal paths. A typical 2.5D system-in- package (SiP) ap- plication will require interconnecting two or more uncased chiplet die elements within a single pack- age outline, typical of that illustrated in Figure 2. D ES I G N E R 'S N OT E B O O K TABLE 1: PROJECTED CHIPLET TERMINAL-TO-LAND DIAMETER Figure 2: 2.5D Interposer enables close interconnect of related functions.