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APRIL 2026 I I-CONNECT007 MAGAZINE 71 Material supply is another structural bottleneck. Local production of laminates and specialty chemi- cals remains limited, forcing reliance on imported advanced materials such as low-CTE fiberglass fabrics, ultra-thin copper foils, specialty resins, and prepregs. Equipment support is similarly con- strained, with high service costs due to reliance on overseas engineering teams. The result is a widening gap between Tier-1 suppliers with access to materials, equipment, and capital, and newer entrants struggling to achieve sustainable margins. China: Still Investing, Still Advancing Crucially, diversification has not slowed advanced investment within mainland China itself: • In December 2025, PCBAIR in Shenzhen launched pilot production of advanced 8-layer glass core PCBs using through-glass via (TGV) technology for AI accelerators, high-speed servers, and optical transceivers. • Jiangmen Yixiang Industrial broke ground in January 2026 on a project targeting annual PCB output of 1 million square meters. • Kinwong recently completed the roof-cap- ping of its $415 million Zhuhai AI server and high-end HDI project, which is expected to add more than 800,000 square meters of high-end HDI capacity by late 2027. • TTM Technologies also announced an ad- ditional $200 million China capacity expan- sion during its February 2026 earnings call, on top of previously allocated investment for data-center computing applications. WUS Printed Circuit: CoWoP and mSAP as a Technology Incubation Platform A particularly notable example of China's continued push into advanced interconnect technology is WUS Printed Circuit's newly announced high-densi- ty optical-electrical PCB project in Jiangsu province, with a planned investment of up to $300 million. Rather than a conventional capacity expansion, WUS has positioned the project as a technology incubation platform spanning R&D, pilot produc- tion, process validation, and eventual commercial deployment. To support this, the company has established a wholly owned subsidiary dedicated to the development of chip-on-wafer-on-platform (CoWoP) and modified semi-additive process (mSAP) manufacturing technologies. CoWoP, often described as "CoWoS without a substrate," represents a significant architectural departure from traditional packaging flows. In this approach, silicon dies and interposers are directly bonded onto a reinforced platform PCB, eliminat- ing the need for conventional organic package substrates and BGA processes. By collapsing multiple packaging layers into a single integrated structure, CoWoP aims to improve signal integrity, power distribution efficiency, and overall system integration—key requirements for next-generation AI servers and high-bandwidth computing plat- forms (Figure 1). Complementing this, WUS is deploying mSAP processes to support ultra-fine line widths and spacing required for high-density interconnect and optical-electrical integration. The project targets the development of optical-copper integrated PCB architectures, enabling tighter signal routing, reduced transmission loss, and improved thermal and electrical performance in high-speed modules. What Is CoWoP? (Chip-on-Wafer-on-Platform) CoWoP (chip-on-wafer-on-platform) is an ad- vanced interconnect and packaging architecture in which silicon dies and interposers are directly bonded onto a reinforced platform PCB, rather than being assembled onto a conventional organ- ic package substrate. By eliminating traditional substrate and BGA layers, CoWoP shortens the electrical path between chips, improving signal integrity, power delivery efficiency, and overall system integration. The approach is designed to support the extreme bandwidth, low latency, and high power density requirements of next-generation AI servers and high-performance computing systems. CoWoP is often described as "CoWoS without a substrate," reflecting its goal of collapsing mul- tiple packaging layers into a single, highly integrat- ed structure.