IPC International Community magazine an association member publication
Issue link: https://iconnect007.uberflip.com/i/1544398
72 I-CONNECT007 MAGAZINE I APRIL 2026 The investment is structured in two phases: 1. With approximately $100 million, phase one focuses on leased pilot production lines for CoWoP and mSAP technologies, supporting early-stage development and qualification. 2. The potential additional $200 million is ex- plicitly conditional on technical validation re- sults and market conditions. WUS has stated that the second phase may be canceled if performance targets are not met. If fully implemented, the project is expected to add approximately 1.3 million units of high-density optical-electrical PCBs per year, with projected annual revenue of around $285 million. However, WUS has emphasized that mass production will only commence once processes meet full indus- trial qualification standards, underscoring a disci- plined, technology-first investment strategy. China remains the focal point for advanced materials, process development, and ecosystem density, particularly as AI packaging complexity continues to rise. Materials: The New Competitive Battleground AI packaging scale is now colliding directly with upstream materials realities. Low-CTE fiberglass cloth and high-frequency HVLP copper foil are experiencing structural sup- ply tightness, with allocation behavior becoming increasingly common and lead times extending well beyond historical norms. Some CCL suppliers CoWoP vs. CoWoS vs. Traditional Substrate-Based Packaging Traditional substrate-based packaging relies on organic substrates and BGA interconnects to connect silicon devices to system boards, offer- ing mature manufacturing but facing increasing limits in bandwidth, warpage control, and power density. CoWoS (Chip-on-Wafer-on-Substrate) improves performance by integrating silicon in- terposers and high-bandwidth memory on an ad- vanced package substrate, but remains complex and cost-intensive. CoWoP (Chip-on-Wafer-on- Platform) removes the substrate layer entirely, di- rectly bonding silicon dies and interposers onto a reinforced platform PCB. This approach reduces interconnect length, lowers signal loss, simplifies stack height, and shifts more integration responsi- bility into the PCB domain—positioning advanced PCB fabrication as a central enabler of future AI system architectures. Figure 1: CoWoP architecture overview.