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64 I-CONNECT007 MAGAZINE I AUGUST 2026 D ES I G N E R 'S N OT E B O O K design engineer with the overall physical specifica- tion for the circuit board, physical outline, the base materials best suited for the application, laminate type and source, and finished plating and coatings (solder mask), as well as establishing the finished board's maximum thickness. The key member of this team, after all, is the PCB design engineer, who is responsible for converting the schematic representation of the product into a tangible, physically functioning PCB ready for assembly. Establishing PCB Design Strategy Before beginning the design process, the PCB de- signer will perform an interconnect capacity analy- sis to establish the basic component area require- ment. In preparation, the PCB design engineer must first gather mechanical outline specifications and electrical data for all active and passive com- ponent parts. From this data, the designer assigns the associated land pattern geometries and pad stack data from the pre-established CAD library. For those components without existing descriptions and pad-stack data, the manufacturer's mechanical and electrical information must be documented to enable creation of the new part(s). To calculate the basic area required for compo- nent placement and circuit interconnect, design- ers must contemplate the land pattern features for mounting the components, define keep-out zones, and establish clearances reserved for the assembly process and post-assembly evaluation, as well as the allowances needed for rework and repair. The final analysis will provide the designer with an esti- mated maximum surface area needed to complete all circuit interconnects. Conductor routing protocols must be established in advance. The space separating via-hole lands, mi- crovia lands, and/or component attachment lands is referred to as "channel width." The channel widths for routing array-configured (BGA, FBGA, WLBGA) semiconductors are calculated using the terminal pitch (center-to-center distance) and the land pattern size. This defines the maximum number of conduc- tors that can be routed between each channel (con- ductors per channel), as demonstrated in Figure 1. The factors that define the limits of circuit conduc- tor routing ability in a substrate are: • Pitch (distance) between land patterns and via-hole lands in the substrate • Number of conductors that can be routed between those features • Maximum number of sub-surface signal layers required Figure 1: Defining channel width for conductor routing paths.