IPC International Community magazine an association member publication
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Implementing blind microvia technology for layer-to- layer interconnect can enable significantly greater circuit routing density, but the build-up process sub- stantially increases the manufacturing complexity since it will affect the number of lamination cycles. Some of the more complex SBU designs, for ex- ample, may require 15 or more lamination cycles. With each lamination cycle, the core materials are subjected to repeated exposure to elevated tem- peratures and high pressure. The concern is that excessive lamination cycles can contribute to ma- terial decomposition, especially a concern for the very thin, multiple layer circuit boards commonly developed for hand-held or portable communi- cation products. These PCBs, in particular, will be more prone to board warping during assembly. Planning PCB Fabrication Although rarely an employee of the actual product development company, a key member of the engi- neering co-design team is the circuit board fabrica- tor, which commonly furnishes practical guidance that helps ensure efficient fabrication processes, maxi- mize yield, minimize cost, and reduce complications. "One of the more common mistakes designers make in creating multilayer structures is that they are often unnecessarily complex." A prominent PCB manufacturer in Silicon Valley made the following observations: 1. Space constraints, due to the increasing number of signal conductors, increased com- ponent density, and number of terminals, will limit the open area on the PCB's surface. This factor can impede the designer's effort to provide the most efficient interconnect circuit routing. Circuit routing becomes increasingly challenging as the spacing between terminal lands decreases. 2. As the component density increases and board surface area becomes restricted, it will force the designer to rely on additional circuit layers for subsurface circuit routing. An excessive increase in circuit layers, however, will impact both fabrication efficiency and manufacturing cost. Challenges facing the fabricator include: • Tolerance control when aligning all layers in the stackup • Maintaining layer-to-layer registration during lamination • Consistent thickness control of the finished board • Avoiding hole breakout of mechanically drilled holes Fabricators should caution designers to exercise re- straint in layer count and in implementing overly com- plex layer-to-layer interconnect schemes. The cost impact attributed to process complexity can adversely affect the competitive position of the end product. Yes, refinement of the board design will require more effort and a little more time, but simplifying the design at this stage of development can reduce fabrication complexity, processing time, and cost. I-CONNECT007 Note: I have learned that establishing a business relationship with the fabricator early in the devel- opment cycle will contribute to both end product reliability and performance. They can assist in selecting the most suitable materials and fabrica- tion method for the application, i.e., subtractive vs. semi-additive circuit definition, conventional multi- layer vs. sequential buildup, mechanical drilling vs. laser microvia processing (stacked or staggered). Their goal is to give you a reliable, high-yield prod- uct at an acceptable cost. Vern Solberg is an indepen- dent technical consultant, specializing in SMT and microelectronics design and manufacturing tech- nology. He is the author of several books, including Design Guidelines for Surface Mount and Microelectronic Technology. To read past columns, click here. D ES I G N E R 'S N OT E B O O K 66 I-CONNECT007 MAGAZINE I AUGUST 2026 D ES I G N E R 'S N OT E B O O K