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AUGUST 2026 I I-CONNECT007 MAGAZINE 75 node is both costly and technically demanding, and requires sophisticated equipment and specialized expertise. For some applications, RDLs with pitches approaching 150 µm and below provide sufficient interconnect density. As previously discussed, tech- nologies such as VeCS are one such approach, as they increase vertical interconnect density while leveraging largely conventional PCB manufacturing processes. Signal and power performance are the key drivers toward adopting advanced process technologies. As the bandwidth/frequencies climb, building a perfect transmission line is a significant challenge. Not Df and Dk values so much as minimizing reflec- tions and GND return paths—tuning impedances to minimise the reflections from component to compo- nent. These optimizations are done in 3D field solvers that address and tune every element in the transmission line: pad sizes, antipads, inductance, capacitive responses, etc. Ultimately, advanced packaging is no longer simply about connecting silicon to a circuit board. It has become a multidisciplinary optimization exer- cise that balances electrical performance, mechan- ical reliability, thermal management, manufactur- ability, and cost. As system complexity increases, innovations in both packaging and PCB fabrication will play an equally important role in enabling the next generation of electronic systems. The Benefits of VeCS for HDI PCB Fabrication VeCS was developed as an alternative means of providing interconnection for large form factor, very high layer count bare PCB products (a minimum of 24 layers). A more traditional HDI approach requires complex builds with multiple lamination cycles (e.g., 24 + 20 layers) to increase the vertical interconnect density per unit area. VeCS avoids the multiple lamination cycles that not only add tremendous time to the product build but also creates potential reliability issues due to material movement and tight cumulative tolerances. VeCS gets around the need for such complex builds, requires less experimentation with new materials, and lessens the need for extraordi- nary efforts toward copper balancing to achieve the surface flatness required to mount large size BGAs. Building such high layer counts in traditional HDI fabrication through many lamination cycles will always be an option for fabricators and will, indeed, be the most appropriate option in specific cases, but that method tends to produce lower yields, especially where the physical dimensions of a typical backplane board built using VeCS are large form factor and only one or two up on a panel. VeCS Slots Allow for Better Plating Coverage HDI fabrication has always had hard limitations due to a microvia's aspect ratio and the limits of wet- chemistry exchange in blind holes when the depth exceeds the hole's diameter, i.e., when aspect ratios are high. Talented industry engineers have been trying to overcome this issue since the mid 1990s, without much success. Hence, the development of VeCS, where a blind slot is created adjacent to a blind via hole, and where the slot size allows for better wet chemistry coverage than just the microvia alone. Slots, or cavi- ties, ranging from 2 mm to greater than 3 mm are created, using a venting hole that is flexible in its position at the bottom of the slot. The venting hole supports power integrity as it is connected to the GND shielding of the slot. During the early design phase of our work, we observed that there is often no hard boundary or limit to the placement of a venting hole, which is beneficial. Another advantage of VeCS is that it helps when you find yourself in a situation where you must compensate for DC and AC losses and match impedances. Naturally, one would want to use thicker and wider traces and create thicker strip- lines. But doing so strictly by manipulating Dk will only get you partway there, and increasing the size of your microvia may not be feasible due to routing constraints. Figure 2 shows a cross-section of two VeCS stacks, where the slots are filled with a high perfor- mance, low loss resin and are overplated. On the right side, this signal shows facing the GND shielding on the left. Also shown at the base of each stack is the zero stub length technology used to stop the signal at the correct layer with no overshoot. This is the same for the bottom GND of the strip line. This enables the area just below the VeCS to be open and available for routing.