I-Connect007 Magazine

I007-Aug-2026

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80 I-CONNECT007 MAGAZINE I AUGUST 2026 to slightly higher frequencies but not where we need to go for the next generation requirements. The cutoff frequency is determined by various elements, but here, we show the LC combination of the vertical connection is the main contributor. If we want to go to higher frequencies, we need to reduce the LC value. For differential pairs, we want to have a certain coupling which influences the C value. Aside from capacitance, the slot itself has a limit in terms of resonance. We plotted a graph showing the main resonance as a function of slot length. The slot length is, of course, related to the component (ball) pitch. If we need to go to higher bandwidths, we need to reduce the slot size. The applies for VeCS, but if we were to build a shielding using stitching vias or stacked micro- vias, this would have a similar response. We see the trend to smaller pitches driven by the required bandwidth. For the large ASICs, we see trends below 0.5 mm, including the connec- tors required to achieve the bandwidths. This will drive PCB technology further and will do so rela- tively quickly. The limit for R-VeCS in terms of physical dimensions (in thick/high layer count boards) is around a 0.5 mm. We have developed a modified approach, X-VeCS, for technologies below 0.6 mm down to 0.12 mm, created using a laser, and often with milling. Reliability Studies and Results IST reliability studies have been performed on every batch of VeCS and R-VeCS product we have manufactured. (X-VeCS is still in the early stage of R&D, so IST reliability studies have not yet been conducted.) Starting with blind VeCS-2, we saw that the hole wall roughness affected the reliability of the copper plating. Even with thick copper, a rough hole wall with fibers sticking out can lower the number of IST cycles. The development of R-VeCS creates a kind of half via which shows a very robust hole wall structure. Figure 7: Resonance as a function of slot length.

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