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96 I-CONNECT007 MAGAZINE I AUGUST 2026 T RO U B L E I N YO U R TA N K To support advanced 2.5D and 3D hetero- geneous integration, product and motherboard designs are now using higher layer counts. As layer counts increase, plated through-holes (PTHs) become deeper and higher in aspect ratio, making it more difficult to achieve a continuous, void-free copper deposit. Drilling these thicker panels and higher aspect ratio vias adds another layer of complexity. Since there are many potential causes of PTH voiding, I'll focus on pre-electroless copper causes, including drilling. Where Are They Coming From? You'll often hear seasoned engineers say that there are so many process steps and variables that influ- ence the success or failure of achieving a continu- ous, void-free copper deposit in the hole. One of the obvious causes of voids, or at least poor copper coverage, is poor drilling. Figure 1 shows voids on the glass bundle fibers. A closer look at this sec- tion shows a very poorly drilled hole wall, with glass bundles protruding from the resin. Many assume the plating process should compen- BY M I C H A E L CA R A N O, G LO BA L E L ECT RO N I C S AS S O C I AT I O N Pre-electroless Causes of Voids Figure 1: Glass fiber bundles are torn out, exposing a deep gouge in the resin.