I-Connect007 Magazine

I007-Aug-2026

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112 I-CONNECT007 MAGAZINE I AUGUST 2026 tion and copper plating are performed. In Steps 3 and 4 the resin is now used to fill the CR slots. After curing, next is the important Step 5 where cross-routes create the vertical interconnects. If vertical traces are going to be used, Step 6, drill/ rout out the back-rout (BR) slots. Then selected vias and slots are resin-filled and cured. In Steps 7 and 8, for pattern plating, the normal process resumes of imaging, plating, stripping and final etching. In the final panel, the board would be solder masked, with any final finishes and fabri- cation. Design Rules To illustrate various routing densities, we like to il- lustrate 0.7 mm pitch because VeCS has a 600% increase over through-hole while HDI has only a 200% improvement. The cross-rout or CR step is also completed. Clearly you can see the glass dielectric removed between the VeCS circuits. This eliminates glass influence for issues like CAF 4 . VeCS-2 design details: The middle part (conduc- tive material) is removed to create two different potentials to the left and right of the slot. Not every position in the slot needs to be processed in this way as it depends on the design. This design method for VeCS is another example of creative concepts. The VeCS-1 with back rout or VeCS-2 differential signals are routed and surrounded by a "racetrack" type ground refer- ence. This nearly creates a complete Faraday Cage for the connections. The SI performance is beneficial for speeds above 10Ghz. Details of the 0.5 mm pitch VeCS breakout using standard VeCS design rules are in referenced in Table 1. Routing will depend on cross-rout slot dimensions. But remember: HDI can only go one or two layers down, while VeCS can go three times deeper. A complete set of design guidelines for VeCS-1 and VeCS-2 (Table 1, p. 114) are broken down into standard, advanced, and in R&D. Additional design illustrations and advice, including tool setups are in the August 2019 issue of PCB007 Magazine 5 . Videos that show the routing of VeCS struc- Figure 5: The VeCS fabrication eight-step process. 8 (Source: NextGin) H A P PY'S T EC H TA L K

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