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114 I-CONNECT007 MAGAZINE I AUGUST 2026 Figure 6: Recommendations for VeCS design rules from Table 1. (Source: NextGin) tures on various EDA tools like Siemens/Mentor, Cadence, Zuken, and Altium are available by contacting NextGin Technology. Electrical Performance Electrical performance is another area (besides CapEx and costs) where VeCS outperforms plated through-hole and HDI. The vertical trace does not have the capacitance and inductance of a via. For extremely high-speed logic, the ability to create shielded differential pairs with minimum distortion is unique. As seen in Figure 7 (p. 116), experimen- tation was conducted to tune vertical traces in the slot such that there is almost no reflection/dis- persion. BestPCB compared simulated vs. actual product measurements. Additional figures show the simulated tuning of a TDR response on VeCS- 2 where we can vary it from a capacitance to an inductance response or make it as "flat" as pos- sible on the NextGin website. Modeling with Simbeor has determined the best performing layer transition. Can we use VeCS to make layer transitions and re-introduce Manhattan routing? First results look interesting. Manhattan/ VeCS routing is an alternative for expensive point- to-point routing for dense boards. VeCS elec- trical performance is discussed in an October H A P PY'S T EC H TA L K