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58 I-CONNECT007 MAGAZINE I AUGUST 2026 achieved, but product reliability is the key driver for VeCS, given the challenges naturally present with stacked microvias. VeCS allows for thicker dielec- trics between layers, contributing to better aspect ratios in some designs. Though some of the indi- vidual techniques of fabricators and their reliability results have, no doubt, advanced in a world where every layer interconnect (ELIC) is becoming more mainstream, the problems associated with them re- main core considerations. Figure 4: Traditional microvia constructions that can be replaced by VeCS. 2 Figure 5: Single-lamination VeCS with a blind slot. 2 From a broader perspective, though, this tech- nique for building HDI PCBs will likely be additive to other technologies currently in use and under de- velopment. When we explore advanced electronics packaging and the advent of the UHDI PCB or sub- strate, all process technologies and techniques at our disposal will come into play—some developed from standard PCB and machining experience, oth- ers adapted from semiconductor manufacturing, as we are seeing in mSAP and SAP processes. In Nolan Johnson's 2020 interview, 4 he asked, "Theoretically, a board could be using VeCS, HDI, and traditional at the same time—three different to- pologies—depending on what you need?" to which Joe Dickson responded, "I expect that. If you look at where the industry is going, as well as the road- map of system-on-chip and FPGA-type technolo- gies, you're trying to do more and more on organic substrates outside of the PCB. That's going to work well as an enabling process to leverage technol- ogy and get it to the forefront for performance now. Right behind that should be some level of value Figure 6: Cross rout results using a standard bit. 3