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82 I-CONNECT007 MAGAZINE I AUGUST 2026 Figure 11: Step 1 of the X-VeCS process: Cross slots machined and pads positioned at ends of the X slots. Figure 12: Step 2 of the X-VeCS process: A blue solder resist layer has been applied, covering the top copper surface and removing the pad structures. Only the surfaces within the two diagonal slots (Slot 1 and 2) are left uncovered and exposed. Figure 13: Two diagonal slots are machined to form an X shape. Four circular BGA pads are positioned at the distal ends of the formed X pattern. Figure 14: Example of X-VeCS showing a differential pair surrounded by shielding. We show the X-VeCS process steps in three major steps. In this example, we do not show the multi-depths per X-VeCS. The depth of the X-VeCS would not go below the bottom GND of the strip- line. With this depth in the design, we can choose to drill the GND positions all the way through the board or sub-assembly. The complexity of X-VeCS is not as much in processing as in the design. We use traditional machines and processes to build VeCS. Equipment needs to be set up for the specific task, but that is not different from traditional processes. For the people starting with it, you can always contact us for questions. For a fee, we can lead projects, perform design, and assist on the side in process set-up for these activities. Acknowledgements I want to thank WUSTEC for their years of cooperation in developing VeCS tech- nology. In cooperation with OEMs and ODMs, they are becoming a centre of ex- pertise for high bandwidth applications in signal in- tegrity and power integrity. I-CONNECT007 Joan Tourné