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June 2014 • SMT Magazine 27 be seen at the LED-in-cavity set-ups, followed by the IMS variants. However, it must not be withheld that an insulation layer between heat sink and semiconductor is frequently unavoidable. An insulating layer between the copper layer and the heat sink is also possible for the LED-in-cavity solution but would also increase the thermal resistance. Conventional FR-4 PCBs with thermal optimized via technol- ogy have higher thermal resistances but proved to be attractive and cost effective variants at least for the mid-power range. Advanced Thermal Management Solutions: Cu-filled Thermal vias Thermal vias are employed since a long time to improve the heat transfer between the two sides of the PCB and to couple heat spread- ing copper areas. Because of the fact that ther- mal vias are normally hollow cylinders, solder can be soaked by the vias as mentioned above and, therefore, components are frequently not directly placed on top of the via array. Excep- tions are large high-power components where enough solder can be applied without the risk of critical voids forming underneath the com- ponent. This problem can be fully avoided if vias are fully filled with copper using a reverse plating process [8] . This can also help to increase the heat transfer area dramatically as can be shown by the following simple consideration. Let us compare the cross section of a hol- low via (Ahollow) with the one of a filled via (Afilled) an average copper cross section ratio b can be calculated above in equation 6. Herein d denotes the via diameter and a the via copper plating thickness. For example, for a via with d = 200 µm and a = 30 µm b = 1,96 which clearly shows that by using filled vias the thermal resistance between top and bottom side can be cut in half. Module Build-up and Thermal Simulations For an investigation of the effectiveness of the filled-via approach a setup according to Figure 16(a) is considered. A LED-chip of 300 µm thickness and 1 x 1 mm² lateral dimen- sions is soldered by Au80Sn-solder onto a bismaleimide triazine (BT) submount (3 x 3 mm²) that is copper coated (35 µm) on both sides forming the thermally relevant structure of the LED submount. Filled vias (d = 200 µm, n = 20) connect top and bottom side of the sub- mount (Figure 16b). This submount is soldered with Sn96Ag solder onto an IMS carrier (10 x 10 mm²) acting as heat spreader and heat sink interface. The solder layers were not modeled (omitted) because the temperature drop caused by the heat flow would be less than 50 mK. The aluminum part of the IMS was replaced by a constant temperature boundary condi- tion. Table 2 lists the thermal properties of the materials inside the model. The simulation results show that it is highly beneficial to use filled vias to reduce the resis- tance of the thermal path. The component can figure 16: a) Chip carrier module build-up; b) cross section of chip carrier. (6) ADvAnCeD THeRMAL MAnAgeMenT SOLuTIOnS continues feaTure