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28 SMT Magazine • June 2014 be placed directly on top of the vias without any problems with insufficient solder (e.g., be- cause of solder sucked up by the copper clad via hole). However, experience gained from manufacturing makes it clear, that via-filling is not always perfect and dimples on the surface can occur. Such an air void inside the solder layer beneath the chip is shown in Figure Table 2: Material properties of components used for finite element model. figure 17: Chip carrier design and first results of thermal simulation: a) 20 vias, d = 200 µm; b) 24 vias, d = 150 µm. Table 3: Maximum temperature and thermal resistance with different thermal via setups. ADvAnCeD THeRMAL MAnAgeMenT SOLuTIOnS continues feaTure