Issue link: https://iconnect007.uberflip.com/i/652863
March 2016 • The PCB Design Magazine 13 the top 10 Ways designers can increase profits traces to meet impedances, and he therefore has to look at altering dielectric. To add insult to injury, should you have a higher copper weight for the inner layers, it may not be an option to reduce dielectric at all! Our recommendation is to consult your chosen fabricator prior to trace layout for any tight impedances (traces .004" and less) to en- sure they can meet your desired impedance. Next, consider the speed. If the literature is showing 4.5Dk at 1Mhz and you know this product will be running at higher speeds, such as 5, 10 or even 20 Ghz, understand the Dk will be driving WAY down. You may be looking at something closer to 3.8 Dk at 5Ghz. Again, the mismatch will affect the impedance. 7. Panelization Requirements If you know where your board will be as- sembled and they have specific panel require- ments for tab placement, tooling hole size and placement, fiducial size and placement, ad- ditional panel text or targets you or they may provide a sub-panel drawing to the fabricator. If you do not, and it is acceptable for your chosen fabricator to sub-panelize a given part for you, understand this: While fabricators are generally very good at assosciating breakaway rails with standard .125" tooling holes and .040"-.060" fi- ducials for auto-insertion devices, should there be a part overhang concern or tab placement concern, it should be communicated to the fab- ricator at the time of quote. No one likes to redo a panelization after "check plots" have been sent by a fabricator; it takes additional time and additional cost to be "re-CAMmed" to add or modify sub panel features. So if you do have specific locations where tabs cannot be placed based on feature proxim- ity or edge plate concerns or specific fiducial siz- es based on your assemblers preferance, be sure to communicate this with your chosen fabrica- tor at the time of quote. 6. Specifying Filled Vias Many of today's products require via fill with either epoxy, silver epoxy, copper epoxy or sometimes even solid plated copper fill. It used to be that if you needed the vias in the region of a BGA exposed on one side of the board and covered on the other, at 1 mm and .8 mm pitch, the vias could be plugged with sol- dermask in lieu of epoxy fill without too much issue. But today with .5 mm and .4 mm pitch de- vices, the same vias now need to be either ep- oxy-filled or conductive epoxy-filled depending on whether or not the vias were being used in any thermal management capacity. Much like with the impedance statement earlier, you may not want to simply specify the location of filled vias by their component names. Make them a unique size. This way you can specify "All .xxx holes to be epoxy-filled and planarized." Or if you are using that same via size where you DO NOT need epoxy fill, create a separate drill file containing only those vioas to be filled. This eliminates guesswork on the side of the fabricator, again speeding things up, minimizing costly revisions and cutting cost. 5. Let's Talk Tolerances What are typical drill tolerances? For most fabricators here in the US that use inch mea- surements for tolerances, we typically say +/- .003" for plated holes and slots and +/-.002" for non-plated holes and slots. Are there situations where these would not be applicable but still possible at a fab level? Yes. Let me give you an example. Let's say the plated holes in question are to be used for a "press-fit" device and the literature says you need +/-.002", this does not fall into the +/-.003" that is standard, but is still fairly common in the industry and IS possible at the fab level. Or let's say the holes are vias. As true vias (not part of a plug-in component), they can be specified as +.003" minus the enire hole size. This is particularly useful if space is limited and tells the fabricator you do not care if they are smaller, as long as they provide good continuity. 4. Avoid Multiple Changes Whether for a quote or a review, try to avoid multiple changes. If you have decided on a giv- en material family, attempt to stick to a mate- rial within that family. If the end-user has not yet decided whether or not a given impedance structure will be co-planar, for example, or even