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26 The PCB Design Magazine • March 2016 longer have the luxury of building a prototype, testing and then revising the approach where necessary. Virtual prototyping, including signal and power integrity, thermal analysis, DFM and 3D interference validation, impart fewer design spins and are essential for design efficiency. 3D interference validation is shown in Figure 1. 3D clearances can be setup then the 3D clearance checking displays violations and automatically zooms in on the selected violation. Entry-level tools tend to rely on the skills of the engineer and PCB designer to detect possible issues as they arise during the design process. However, these days a more constraint-driven, correct-by-construction approach is required for complex designs. Once the rules are estab- lished, they will be followed by downstream tools and validated to conform by the various design rule checkers (DRCs). Figure 2 illustrates typical constraints plan- ning and definition for a high-speed DDR2 & 3 design. The constraints should be defined at the schematic level and flow through to the layout process. The advantage of this approach is that the engineer can convey his intent, to the PCB designer, without misinterpretation. Alterna- tively, the independent engineer (the guy who does everything) can manage the constraints, throughout the design process, using the same consistent management tool. Also, the reuse of constraints from a previous proven design not only ensures consistent rules but also minimiz- es the possibility of errors. Net classes are used to organize and speed-up the definition of routing constraints for nets with similar properties. For each net class, the layers allowed for routing, the corresponding trace width range for these layers, and the via types allowed can be defined. For differential pairs, a layer-dependent differential pair gap can be de - fined based on the calculated impedance to en- sure uniform impedance across all layers. Proper grouping and definition of net classes and constraint classes in the early stages of the de- sign process simplifies constraint definition and management significantly. Grouped constraints can increase layout efficiency, reducing design time and, ultimately, lower PCB design costs. Pre-layout simulation allows the designer to predict and eliminate signal and power integrity, crosstalk and EMC issues early in the design pro- cess. This is the most cost-effective way to de- sign a board with fewer iterations, rather than starting with the post-layout simulation. One the need for speed: strategies for design efficiency Figure 3: DDR3 memory address net topology exported to LineSim.