Issue link: https://iconnect007.uberflip.com/i/652863
March 2016 • The PCB Design Magazine 27 the need for speed: strategies for design efficiency can quickly simulate complex interconnect sce- narios including ICs, transmission lines, connec- tors and passive components to identify which scenario is best suited to a particular design. An integrated correct-by-construction com- ponent library also ensures that once a part is defined, the symbol, cell and part mappings will be in sync. This approach eliminates a ma- jor cause of design iterations commonly found in netlist driven design paradigms. Apart from the use of signal and power in- tegrity analysis tools, most designers still rely on eye-balling to pick up many inconsistencies in the layout. HyperLynx DRC, for instance, can verify complex design rules that are not easily simulated, such as EMC constraints. With sup- port for DRCs of such items as traces crossing split planes, reference plane changes, shielding and via checks, one can quickly detect and rec- tify issues that may later on causes intermittent signal and power integrity issues. The DRCs can also be customized to allow users to create con- straints for any check that they may otherwise perform manually eliminating human error. Today's high-performance processors, with sub-nanosecond switching times, use low DC voltages with high transient currents and high clock frequencies in order to minimize the power consumption and hence heat dissipated. However, fast rise times, low output buffer im- pedance an d the simultaneous switching of bus- ses create high transient currents in the power Figure 4: Thermal simulation of hotspots on the bottom of the PCB.