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50 DESIGN007 MAGAZINE I FEBRUARY 2024 With the trend to smaller feature sizes and faster signal rise times, embedded capacitance material (ECM) is becoming a cost-effective solution to improve power integrity further. is technology provides an effective approach for decoupling high-performance ICs while reducing electromagnetic interference. Plane pair cavity resonances contribute to emissions. Smaller plane separation implies less area of equivalent magnetic current at the plane pair edge, or equivalently less local fring- ing field volume, and therefore lower emissions for a given field strength. However, the smaller the plane separation, the higher the Q of the cavity can be, resulting in higher field strength at the plane pair edges. Embedded capacitance material comprises copper-clad laminates with very thin dielectric thickness and high dielectric constant. ese materials can replace the standard power and ground planes, thereby providing additional capacitance embedded into the PCB stackup. Embedded capacitance materials are defined and described in IPC 4821, Specification for Embedded Passive Device Capacitor Materials for Rigid and Multilayer Printed Boards. Contrary to normal high-speed design prac- tices, the material has a high dielectric con- stant (Dk), which increases capacitance, and a high dissipation factor (Df ), which dampens electromagnetic energy through the relatively high loss of the material. Embedded capacitance technology has a very thin dielectric layer (0.24–2.0 mil), which pro- vides distributive decoupling capacitance and takes the place of conventional discrete decou- pling capacitors over 1 GHz. ese ultra-thin lam- inates replace conventional power and ground planes and have excellent stability of dielectric constant and dielectric loss up to 15 GHz. e thinner layers of ECM also significantly reduce the capacitor mounting inductance. e embedded capacitor layer can be placed anywhere in the board stackup (including outer layers if desired). Multiple layers can be used to increase capacitance and lower induc- tance. Placing the embedded capacitor layer closer to the surface (closer to the ICs as in Fig- ure 2) will reduce via inductance and make the capacitance material more effective, especially Figure 2: High-speed 12-layer stackup using 3M, ECM of 0.24 mil core thickness.