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FEBRUARY 2024 I DESIGN007 MAGAZINE 51 at high frequencies. If more than one embed- ded capacitance layer is used, they should be distributed so there is a balanced stackup and board warping is kept to a minimum. is also provides decoupling of ICs on the bottom side of the PCB. e ZBC-2000 laminate uses a single ply of either 106 or 6060 style prepreg, yielding a dielectric thickness aer lamination of 2 mils as measured by cross-sectioning. Similarly, ZBC- 1000 results in a 1-mil dielectric distributed capacitance material. FaradFlex and Interra bur- ied capacitance products utilize a durable resin system for non-reinforced dielectrics for 1 mil thickness and below. is eliminates the skew associated with the fiber-weave effect in stan- dard materials. Also, with a product range of up to 20 nF per square inch in capacitance den- sity, 3M ECM is the highest capacitance density embedded capacitance material on the market. ese ultra-thin laminates allow a signifi- cant layer count reduction in PCBs with bet- ter signal performance. With a high withstand- ing voltage, these glass-free films change the design rules for via diameter and trace width, while still conforming to the manufacturing needs of the fab. ree traces between vias, at a 0.4 mm pitch, are possible and very manufac- turable, according to Integral Technology. It is a common belief that solid power and ground planes act as large, perfect, lumped element capacitors. However, they actually encompass a distributed system of surprising complexity. e distinction between a lumped element and a distributed system involves the relationship between the time delay of the sys- tem and the rise time of the signals. For instance, for a PCB of six square inches, the signals entrapped between the VCC and GND planes create a standing wave, resonat- ing as they reflect from side-to-side, and have a delay time of about 1 ns. If the rise-time of the signal is 5 ns, the lumped condition is satisfied. However, with a much faster rise-time or if the plane is very small (typically one-inch square), then the driver perceives the VCC and GND structure as a distributed object with signifi- cant delay. is oen occurs on mixed signal/ power layers. is delay causes two issues: 1. During the rising and falling edge, only the portion of the planes and decoupling capacitors located within the close vicinity of the driver can react before the edge has vanished. is frequently results in the noise spike being larger than anticipated. Table 1: Embedded capacitor materials available in the ICD dielectric materials library