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90 SMT007 MAGAZINE I MAY 2024 mold ratio and higher warpage at elevated tem- peratures. In particular, a larger sample with higher die-to-mold ratio and a smaller sample with a lower die-to-mold ratio would be valu- able, though possibly difficult to find. Acknowledgments e author would like to acknowledge Brian Roggeman of Qualcomm for help in multiple aspects of the study and data analysis, Han Wu of HB Fuller for supporting MSL conditioning, Leon Weaver and Charly Olson of Akrometrix for thermal shadow moiré testing, and Ryan Curry of Akrometrix for applications support and editing. SMT007 References 1. J-STD-020E, "Joint IPC/JEDEC Standard for Moisture/Reflow Sensitivity Classification for Non- hermetic Surface-Mount Devices," IPC/JEDEC Solid State Technology Association, December 2014. 2. J-STD-033D, "Joint IPC/JEDEC Standard for Handling, Packaging, Shipping, and Use of Mois- ture/Reflow Sensitive Surface-Mount Devices," IPC/ JEDEC Solid State Technology Association, April 2018. 3. JESD22-A120, "Test Method for the Measure- ment of Moisture Diffusivity and Water Solubility in Organic Materials Used in Integrated Circuits," JEDEC Solid State Technology Association, July 2014. 4. "Case Studies in Evaluation of Moisture Sen- sitive Level (MSL) and Reliability of Devices of High Reliability (High-Rel) Applications," by S.R. Martell, Proceedings of SMTA International, p 70-75, 2003. 5. "Recent Trends of Package Warpage Charac- teristic," by W. Loh, R. Kulterman, T. Purdie, H. Fu, and M. Tsuriya, International Conference on Elec- tronics Packaging (ICEP) 2015. 6. Microelectronics Reliability, P. Alpern, K.C. Lee, R. Tilgner, Vol 44, Issues 9-11, p 1293-1297. Amster- dam: Elsevier, 2004. 7. JESD22-B112B, "Package Warpage Measure- ment of Surface-Mount Integrated Circuits at Ele- vated Temperature," JEDEC Solid State Technology Association, August 2018. 8. JEITA ED-7306, "Measurement methods of package warpage at elevated temperature and the maximum permissible warpage," Japan Electron- ics and Information Technology Association, March 2007. 9. IPC-7095D, "Design and Assembly Process Implementation for Ball Grid Arrays (BGAs)," IPC, June 2018. 10. "Reflow Warpage Induced Interconnect Gaps between Package/PCB and PoP Top/Bottom Pack- ages," by K. Peng, W. Xu, Z. Qin, L. Feng, L. Lai, W. Koh, Proceedings of ECTC, 2017. 11. "Effect of Package Warpage and Compos- ite CTE on Failure Modes in Board-Level Thermal Cycling," A. Mawer, M. Benson, B. Carpenter, N. Hubble, Proceedings of SMTA International, 2018. 12. "Surface Mount Signed Warpage Case Study; New Methods for Characterizing 3D Shapes Through Reflow Temperatures," N. Hubble, J. Young, J., K. Hartnett, Proceedings of IPC APEX EXPO, 2017. Neil Hubble is president of Akrometrix.