Issue link: https://iconnect007.uberflip.com/i/1533085
30 DESIGN007 MAGAZINE I MARCH 2025 Impedance is at the core of the methodology that is used to solve signal integrity issues. If you extract the interconnect topology (Figure 1) from a PCB layout to a free-form schematic model, the result can be terrifying—not quite that simple DDR address trace that was routed. In this case, any of the 15 individual transmis- sion lines that form just one DDR signal inter- connect can create issues if incorrectly routed. In source-synchronous interfaces like DDR memory, it's crucial for data signals to reach the load simultaneously with the data strobe. is synchronization is achieved by match- ing the delays of all signals between data lanes and strobes within a certain tolerance. While address and command signals are also matched to the clock, they have a less stringent toler- ance. However, matching the lengths doesn't ensure uniform propagation delay for each sig- nal. Traces routed to equal lengths on different layers exhibit different delays, especially when comparing microstrip (outer layers) to strip- line (inner layers), due to the differing dielec- tric materials (including air) surrounding the traces. Hence, buses and associated control signals should all be routed on the same layer or a symmetric layer of the stackup. However, if they are routed on different layers then they must be routed to matched delay. Typically, serpentine traces (or meander lines) are used to match the length of these critical signals, assuming that the extra length of the serpentine pattern will be electrically the same as a straight trace and no parasitics are introduced. But as technology advances and demands for smaller traces with less clearance and faster rise times become more the norm, this assumption may no longer be valid. Con- trary to what you may believe, the propagation delay of a serpentine trace is less than the delay through an equivalent-length straight trace. e meandering signal is sped up because a portion of the signal will propagate perpendic- ular to the serpentine. is also varies with the type of serpentine pattern used. For instance, the "switch-back" serpentine pattern may Figure 1: Free-form schematic model of a DDR address signal (simulated in HyperLynx).