Issue link: https://iconnect007.uberflip.com/i/1533085
MARCH 2025 I DESIGN007 MAGAZINE 31 feature long parallel segments spaced closely together causing multiple instances of signal coupling throughout the serpentine pattern. is self-coupling, involving both forward and reverse crosstalk, effectively shortens the elec- trical path. In Figure 2, the green waveform is the driver. Red is the straight (reference) trace. Blue is the serpentine trace which leads the reference trace by 150 ps despite being the same length. e peak and trough in the blue serpentine trace (between 4 to 6 ns) are the reverse and forward crosstalk, respectively, from the close segment coupling. In this case, matching the delay of the traces may not be sufficient and the resultant overall delay of 150 ps may not be within margins. Clock delay is another common issue I encounter regularly. e clock (or strobe) sig- nal in source-synchronous interfaces should have the longest delay within the bus group. Synchronous interfaces are uniquely immune to crosstalk, provided the data signals are clocked aer they have settled—during the hold time. However, if the clock delay is shorter than the data signal delay, it may sync during the setup time and crosstalk may arise. Route the clock/ strobe last to ensure it is the longest trace. Ground pours can also affect the impedance of a critical trace. Some PCB designers do this habitually, claiming various reasons for its use. Additionally, many reference designs provided by chip manufacturers employ this ground pour technique. However, placing a copper Figure 2: Closely coupled serpentine trace versus straight trace (microstrip). Figure 3: Symmetric coplanar waveguide with ground plane (simulated in iCD CPW Planner).