Issue link: https://iconnect007.uberflip.com/i/1533085
MARCH 2025 I DESIGN007 MAGAZINE 33 ties is to follow the signal path and imagine the return path closely coupled on the near- est plane. If there are multiple planes present in the layer stack, then the displacement cur- rent will still take the path of least inductance and follow closely coupled to the signal trace. If a discontinuity interrupts this return flow, then the return current will be forced into a distant plane where it has a clear run creating increased inductance. Crosstalk can occur either between traces on the same layer or through broadside coupling between traces on adjacent layers (Figure 4). is coupling is three-dimensional. Broadside coupling is harder to detect (particularly on built-up outer layers) because we typically focus on trace clearances when assessing crosstalk, but a simulator can identify this issue. Traces routed in parallel and broadside experience more crosstalk than those routed side-by-side due to the larger coupling area and tighter spac- ing. Hence, it's good practice to route adjacent signal layers orthogonally to each other in the stackup to minimize the coupling region. When performing interactive routing, PCB designers oen group signals for aesthetic rea- sons, showcasing their artistic side. However, while this might look tidy and organized, it might not yield the best performance. Beyond the previously discussed synchronous buses, it is advisable to space unrelated critical trace segments by three times the trace width, if possible. Alternatively, if real estate is limited, the trace-to-plane height in the stackup can be reduced to increase coupling. High-speed PCB design involves many con- siderations to ensure reliable performance and signal integrity. Impedance matching remains the core of solving signal integrity issues. By focusing on these critical considerations, PCB designers can create successful high-speed designs that meet the demands of modern technology and perform reliably. Key Points • e most critical factor in high-speed PCB design is the impedance of the interconnect. • Impedance is at the core of the methodology that is used to solve signal integrity issues. • Traces routed to equal lengths on different layers exhibit different delays. Figure 4: Broadside coupled crosstalk (simulated in HyperLynx). " High-speed PCB design involves many considerations to ensure reliable performance and signal integrity. "