Issue link: https://iconnect007.uberflip.com/i/1541169
14 DESIGN007 MAGAZINE I NOVEMBER 2025 either GND or a 1.2 V power plane as a reference (return) plane since this is the nominal power loop where the current is drawn from. Experiment 6: Board Area Smaller Than the Effective Area For this experiment, the board area will be made considerably smaller: 2 in 2 (1.41 x 1.41 in). The stack- up has been modified back to 3 mil spacing, with a dielectric constant of 4.3, and the current sink and VRM connected to just Layer 2 as previously. Figure 8 shows the results of the simulation. Here we see the peak noise voltage is worse at the edges of the board (129.4 mV) vs. at the current sink (106 mV). The board geometry is also playing a role as there are modal resonances occurring differently than with the larger board. We can conclude that both decreasing the dielec- tric spacing between the layers and using additional planes will decrease our noise voltage by increas- ing the capacitance of the system. What about increasing the dielectric constant to something higher? Recalling the earlier experi- ment, increasing the dielectric constant negatively affected the available capacitance by shrinking the effective decoupling radius. However, if the plane area is smaller than the effective area, then the capacitance is not being fully utilized by the current sink. Decreasing the effective area by increasing the dielectric constant will increase the available capacitance and should lower the noise voltage. Solving Equation 2 for the dielectric constant using the appropriate radius yields ~14, which tells us we can increase the dielectric constant all the way up to 14. Doing so will fully utilize the plane area in a way that maximizes the capacitance and lowers the noise voltage. The results are shown in Figure 9. We notice right away that the noise voltage at the current sink has not changed much (delta of ~12 mV), but the noise voltage at the plane edges has decreased by 66 mV. In this case, local decoupling of the current sink should also help suppress the noise voltage. Final experiments yield a noise voltage of only 22 mV at the plane edges and 33.5 mV at the current sink when using 1-mil dielectrics, and 39.3 mV at the current sink and 23 mV at the edges of the PCB when adding an additional power plane cavity. The best scenario for this experiment is to change the power plane spacing to 1 mil as well as add an addi- tional layer when using the high dielectric material. In this case, the noise voltage simulates as only 15.5 F i g u re 8 : T h e re s u l t s of E x p e r i m e nt 6. T h e tot a l b o a rd a re a i s c o n s i d e ra b l y s m a l l e r t h a n t h e ef fe ct i ve a re a . T h e p e a k n o i s e vo l t a g e i s 1 2 9.4 m V, l o c ate d at t h e e d g e s , w h e re a s t h e vo l t a g e at t h e c u r re nt s i n k i s a p p rox i m ate l y 1 0 6 m V. ▼ F i g u re 9 : T h e re s u l t s of E x p e r i m e nt 6 w h e n a d j u st i n g t h e d i e l e ct r i c c o n st a nt to 1 4. T h e p e a k n o i s e vo l t a g e h a s d e c re a s e d n e a r t h e c o r n e rs by 6 6 m V, b u t o n l y to 9 3 . 2 m V at t h e c u r re nt s i n k . ▼