Issue link: https://iconnect007.uberflip.com/i/1520213
42 SMT007 MAGAZINE I MAY 2024 Are you suggesting that passives could be included inside the advanced package along with the chiplet architecture? Absolutely. is is already happening, and it's a big benefit for the high-power demands, like voltage regulation and controlling droop. Inte- grating passives in these advanced packages offers a significant benefit. There's a historical push-and-pull cycle in printed circuit boards: You get all this com- plexity on the boards from cutting-edge chip- sets, then those chipsets move on to a single chip, and the board simplifies. at's right. It's all related to becoming more compact and getting more components into a smaller volume. Five years from now, how will the overall sup- ply chain—your ecosystem—look different in response to these new chiplet architectures? e chiplet ecosystem will evolve and mature. at means these elements will be better inter- connected. Right now, there are a lot of very independent players. But as chiplet archi- tectures gain momentum, these layers will become more integrated. It's important to understand that a chiplet architecture is a very complex system. It involves a lot of unique challenges that are not pres- ent when designing a monolithic chip with a single chip module. So, these various stakeholders must work together to form a unified flow to realize these kinds of chiplet architectures. At the assembly step, when they're building up the finished product, is that where all those decisions come together? at's right. A number of standards and test procedures would need to be in place at that level to ensure a good final product. Are you involved in the standards definition processes for this area? I'm personally tracking it, while others in IBM and our broader team are heavily involved. Where are the standards being developed that you're watching? ere are a number of different and dispa- rate organizations right now. Interface stan- dards are being driven by consortia, such as the UCIe (Universal Chiplet Interconnect Express); packaging standards are being dis- cussed in different forums. Security is a very ripe area, but those standards are only begin- ning because chiplets from heterogeneous sources present new security and supply chain challenges. Known good die and test method- ologies require standards; IEEE has significant activity in this area. e EDA vendors oen have tools, but they aren't interoperable; that's another area where standards could be bene- ficial to enable the best tool from a particular vendor to be combined with other tools that do a different function. Arvind, thank you so much. ank you. SMT007